3.4.14 ARMCortexA5MPx1CT

ARMCortexA5MPx1CT CPU component. This model is written in C++ and models version r0p0 of the RTL.

ARMCortexA5MPx1CT contains the following CADI targets:

  • ARM_Cortex-A5MP
  • Cluster_ARM_Cortex-A5MP
  • PVCache
  • TlbCadi

ARMCortexA5MPx1CT contains the following MTI components:

Note:

  • The following components also exist:

    • ARMCortexA5MPx2CT.
    • ARMCortexA5MPx4CT.
  • The per-core parameters are preceded by cpun., where n identifies the core (0-3).

Differences between the CT model and RTL implementations

This component has the following differences from the corresponding revision of the RTL implementation:

  • There is a single memory port combining instruction, data, DMA and peripheral access.
  • The GIC does not respect the CFGSDISABLE signal. This leads to some registers being accessible when they must not be.
  • The SCU enable bit is ignored. The SCU is always enabled.
  • The SCU ignores the invalidate all register.
  • The Broadcast TLB or cache operations in this model do not cause other cores in the cluster that are asleep because of Wait For Interrupt (WFI) to wake up.
  • The RR bit in the SCTLR is ignored.
  • The Power Control Register in the system control coprocessor is implemented but writing to it does not change the behavior of the model.
  • When modeling the SCU, coherency operations are represented by a memory write followed by a read to refill from memory, rather than using cache-to-cache transfers.

Caches

This component implements L1 cache as architecturally defined, but does not implement L2 cache. If you require an L2 cache you can add a PL310 Level 2 Cache Controller component.

Debug features

All core, VFP, and CP15 registers are visible in the debugger. The CP14 DSCR register is visible for compatibility with some debuggers. This register has no defined behavior. This component also exports the SCU, Watchdog/Timer and GIC registers.

This component directly supports single-address unconditional instruction breakpoints, unconditional instruction address range breakpoints, and single-address unconditional data breakpoints. The debugger might augment these with more complex combinations of breakpoints.

The model does not support CADI exception breakpoints. Instead, it implements exception breakpoints as register breakpoints on pseudoregisters, named after the exceptions, in the Vectors register group.

This component presents two 4GB views of virtual memory, one as seen from secure mode and one as seen from normal mode.

Additional parameter information

ase-present, vfp present
The ase-present and vfp-present parameters configure the synthesis options:
vfp present and ase present
NEON and VFPv3-D32 supported.
vfp present and ase not present
VFPv3-D16 supported.
vfp not present and ase present
Illegal. Forces vfp-present to true so model has NEON and VFPv3-D32 support.
vfp not present and ase not present
Model has neither NEON nor VFPv3-D32 support.
device-accurate-tlb
Specifying false enables modeling a different number of TLBs if this improves simulation performance. The simulation is architecturally-accurate, but not device-accurate. Architectural accuracy is almost always sufficient. Specify true if device accuracy is required.
PERIPHBASE
If you are using this component on a VE model platform, this parameter is set automatically to 0x1F000000 and is not visible in the parameter list.
vfp-enable_at_reset
This is a model-specific behavior with no hardware equivalent.

Table 3-112 Ports

Name Protocol Type Description
acp_s PVBus Slave AXI ACP slave port.
cfgend[1] 2.7.2 Signal protocol Slave This signal if for EE bit initialisation.
cfgnmfi[1] 2.7.2 Signal protocol Slave This signal disables FIQ mask in CPSR.
cfgsdisable 2.7.2 Signal protocol Slave This signal disables write access to some secure Interrupt Controller registers.
clk_in ClockSignal Slave The clock signal connected to the clk_in port is used to determine the rate at which the core executes instructions.
clusterid 2.7.4 Value protocol Slave The port reads the value in CPU ID register field, bits[11:8] of the MPIDR.
cp15sdisable[1] 2.7.2 Signal protocol Slave This signal disables write access to some system control processor registers.
event 2.7.2 Signal protocol Peer This peer port of event input (and output) is for wakeup from WFE.
filteren 2.7.2 Signal protocol Slave This signal enables filtering of address ranges between master bus ports.
filterend 2.7.4 Value protocol Slave This port sets end of region mapped to pvbus_m1.
filterstart 2.7.4 Value protocol Slave This port sets start of region mapped to pvbus_m1.
fiq[1] 2.7.2 Signal protocol Slave This signal drives the CPU's fast-interrupt handling.
fiqout[1] 2.7.2 Signal protocol Master This signal exports internal VGIC FIQ signal to the CPU.
ints[224] 2.7.2 Signal protocol Slave This signal drives the CPU's fast-interrupt handling.
irq[1] 2.7.2 Signal protocol Slave This signal drives the CPU's interrupt handling.
irqout[1] 2.7.2 Signal protocol Master This signal exports internal VGIC IRQ signal to the CPU.
periphbase 2.7.4 Value protocol Slave This port sets the base address of private peripheral region.
periphclk_in ClockSignal Slave The timer and the watchdog take need a clk that is scaled down atleast by factor of two.
periphreset 2.7.2 Signal protocol Slave This signal resets timer and interrupt controller.
pmuirq[1] 2.7.2 Signal protocol Master Interrupt signal from performance monitoring unit.
pvbus_m0 PVBus Master AXI master 0 bus master channel.
pvbus_m1 PVBus Master AXI master 1 bus master channel.
pwrctli[1] 2.7.4 Value protocol Slave This port sets reset value for scu CPU status register.
pwrctlo[1] 2.7.4 Value protocol Master This port sends scu CPU status register bits.
reset[1] 2.7.2 Signal protocol Slave Raising this signal will put the core into reset mode.
scureset 2.7.2 Signal protocol Slave This signal resets SCU.
smpnamp[1] 2.7.2 Signal protocol Master This signals AMP or SMP mode for each Cortex-A5 processor.
standbywfe[1] 2.7.2 Signal protocol Master This signal indicates if a core is in WFE state.
standbywfi[1] 2.7.2 Signal protocol Master This signal indicates if a core is in WFI state.
teinit[1] 2.7.2 Signal protocol Slave This signal provides default exception handling state.
ticks[1] 2.6.3 InstructionCount protocol Master This port should be connected to one of the two ticks ports on a 'visualisation' component, in order to display a running instruction count.
vinithi[1] 2.7.2 Signal protocol Slave This signal controls of the location of the exception vectors at reset.
virtio_s PVBus Slave The virtio coherent port, hooks directly into the L2 system and becomes coherent (assuming attributes are set correctly).
wdreset[1] 2.7.2 Signal protocol Slave This signal resets individual watchdog.
wdresetreq[1] 2.7.2 Signal protocol Master This signal resets rest of the CA5MP system.

Table 3-113 Parameters for ARM_Cortex-A5MP

Name Type Default value Description
cpu0.CFGEND bool 0x0 Initialize to BE8 endianness
cpu0.CFGNMFI bool 0x0 Enable nonmaskable FIQ interrupts on startup
cpu0.CP15SDISABLE bool 0x0 Initialize to disable access to some CP15 registers
cpu0.POWERCTLI int 0x0 Default power control state for processor
cpu0.SMPnAMP bool 0x0 Set whether the processor is part of a coherent domain
cpu0.TEINIT bool 0x0 T32 exception enable. The default has exceptions including reset handled in A32 state
cpu0.VINITHI bool 0x0 Initialize with high vectors enabled
cpu0.ase-present bool 0x1 Set whether model has NEON support
cpu0.dcache-size int 0x8000 Set D-cache size in bytes
cpu0.icache-size int 0x8000 Set I-cache size in bytes
cpu0.min_sync_level int 0x0 force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
cpu0.semihosting-ARM_HLT int 0xf000 ARM HLT number for semihosting
cpu0.semihosting-ARM_SVC int 0x123456 ARM SVC number for semihosting
cpu0.semihosting-Thumb_HLT int 0x3c Thumb HLT number for semihosting
cpu0.semihosting-Thumb_SVC int 0xab Thumb SVC number for semihosting
cpu0.semihosting-cmd_line string "" Command line available to semihosting SVC calls
cpu0.semihosting-cwd string "" Base directory for semihosting file access.
cpu0.semihosting-enable bool 0x1 Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false
cpu0.semihosting-heap_base int 0x0 Virtual address of heap base
cpu0.semihosting-heap_limit int 0xf000000 Virtual address of top of heap
cpu0.semihosting-hlt-enable bool 0x0 Enable semihosting HLT traps. Applications that use HLT semihosting must set this parameter to true and the semihosting-enable parameter to true
cpu0.semihosting-stack_base int 0x10000000 Virtual address of base of descending stack
cpu0.semihosting-stack_limit int 0xf000000 Virtual address of stack limit
cpu0.vfp-enable_at_reset bool 0x0 Enable coprocessor access and VFP at reset
cpu0.vfp-present bool 0x1 Set whether the model has VFP support

Table 3-114 Parameters for Cluster_ARM_Cortex-A5MP

Name Type Default value Description
CFGSDISABLE bool 0x0 Disable some accesses to GIC registers
CLUSTER_ID int 0x0 Processor cluster ID value
FILTEREN bool 0x0 Enable filtering of accesses through pvbus_m0
FILTEREND int 0x0 End of region filtered to pvbus_m0
FILTERSTART int 0x0 Base of region filtered to pvbus_m0
PERIPHBASE int 0x13080000 Base address of peripheral memory space
cpi_div int 0x1 Divider for calculating CPI (Cycles Per Instruction)
cpi_mul int 0x1 Multiplier for calculating CPI (Cycles Per Instruction)
dcache-hit_latency int 0x0 D-Cache timing annotation latency for hit. Intended to model the tag-lookup time. This is only used when dcache-state_modelled=true.
dcache-maintenance_latency int 0x0 D-Cache timing annotation latency for cache maintenance operations given in total ticks. This is only used when dcache-state_modelled=true.
dcache-miss_latency int 0x0 D-Cache timing annotation latency for miss. Intended to model the time for failed tag-lookup and allocation of intermediate buffers. This is only used when dcache-state_modelled=true.
dcache-read_access_latency int 0x0 D-Cache timing annotation latency for read accesses given in ticks per access. If this parameter is non-zero, per-access latencies will be used instead of per-byte even if dcache-read_latency is set. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus, this is only used when dcache-state_modelled=true.
dcache-read_latency int 0x0 D-Cache timing annotation latency for read accesses given in ticks per byte accessed.dcache-read_access_latency must be set to 0 for per-byte latencies to be applied. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus. This is only used when dcache-state_modelled=true.
dcache-snoop_data_transfer_latency int 0x0 D-Cache timing annotation latency for received snoop accesses that perform a data transfer given in ticks per byte accessed. This is only used when dcache-state_modelled=true.
dcache-state_modelled bool 0x0 Set whether D-cache has stateful implementation
dcache-write_access_latency int 0x0 D-Cache timing annotation latency for write accesses given in ticks per access. If this parameter is non-zero, per-access latencies will be used instead of per-byte even if dcache-write_latency is set. This is only used when dcache-state_modelled=true.
dcache-write_latency int 0x0 D-Cache timing annotation latency for write accesses given in ticks per byte accessed. dcache-write_access_latency must be set to 0 for per-byte latencies to be applied. This is only used when dcache-state_modelled=true.
device-accurate-tlb bool 0x0 Specify whether all TLBs are modeled
dic-spi_count int 0x40 Number of shared peripheral interrupts implemented
icache-hit_latency int 0x0 I-Cache timing annotation latency for hit. Intended to model the tag-lookup time. This is only used when icache-state_modelled=true.
icache-maintenance_latency int 0x0 I-Cache timing annotation latency for cache maintenance operations given in total ticks. This is only used when icache-state_modelled=true.
icache-miss_latency int 0x0 I-Cache timing annotation latency for miss. Intended to model the time for failed tag-lookup and allocation of intermediate buffers. This is only used when icache-state_modelled=true.
icache-read_access_latency int 0x0 I-Cache timing annotation latency for read accesses given in ticks per access. If this parameter is non-zero, per-access latencies will be used instead of per-byte even if icache-read_latency is set. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus, this is only used when icache-state_modelled=true.
icache-read_latency int 0x0 I-Cache timing annotation latency for read accesses given in ticks per byte accessed.icache-read_access_latency must be set to 0 for per-byte latencies to be applied. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus. This is only used when icache-state_modelled=true.
icache-state_modelled bool 0x0 Set whether I-cache has stateful implementation
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