3.4.22 ARMCortexA8CT

ARMCortexA8CT CPU component. This model is written in C++ and models version r2p1 of the RTL.

ARMCortexA8CT contains the following CADI targets:

  • ARM_Cortex-A8
  • PVCache
  • TlbCadi

ARMCortexA8CT contains the following MTI components:

Differences between the CT model and RTL implementations

This component has the following differences from the corresponding revision of the RTL implementation:

  • There is a single memory port combining instruction, data, DMA and peripheral access.
  • The L2 cache write allocate policy is not configurable. It defaults to write-allocate. Writes to the configuration register succeed but are ignored, meaning that data can be unexpectedly stored in the L2 cache.
  • Unaligned accesses with the MMU disabled on the processor do not cause data aborts.

Registers

This component provides the registers that the Technical Reference Manual (TRM) specifies except for the coprocessor 14 registers, the integration and test registers, and the PLE model, which is register based and has no implemented behavior.

These TLB registers do not have working implementations:

  • D-TLB ATTR read/write.
  • D-TLB CAM read/write.
  • D-TLB PA read/write.
  • Normal memory remap register.
  • Primary memory remap register.

This component does not model Level 1 or Level 2 caches. The system coprocessor registers related to cache operations permit cache aware software to work, but in most cases they only check register access permissions:

  • Cache Dirty Status.
  • Data Memory Barrier.
  • Data Write Barrier.
  • ICache/DCache lockdown.
  • ICache/DCache master valid.
  • Invalidate and/or Clean Both Caches.
  • Invalidate and/or Clean Entire ICache/DCache.
  • Invalidate and/or Clean ICache/DCache by Index.
  • Invalidate and/or Clean ICache/DCache by MVA.
  • Level 1 System array debug registers.
  • Level 2 Cache Auxiliary control.
  • Level 2 Cache Lockdown.
  • Level 2 System array debug registers.
  • Prefetch ICache Line.
  • Preload Engine registers.

In addition, the simulation does not distinguish peripheral accesses from data accesses, so it ignores configuration of the peripheral port memory remap register.

Debug features

All core, VFP, and CP15 registers are visible in the debugger. The CP14 DSCR register is visible for compatibility with some debuggers. This register has no defined behavior.

This component directly supports single address unconditional instruction breakpoints, unconditional instruction address range breakpoints, and single address unconditional data breakpoints. The debugger might augment these with more complex combinations of breakpoints.

The model does not support CADI exception breakpoints. Instead, it implements exception breakpoints as register breakpoints on pseudoregisters, named after the exceptions, in the Vectors register group.

This component presents two 4GB views of virtual memory, one as seen from secure mode and one as seen from normal mode.

Additional parameter information

device-accurate-tlb
Specifying false enables modeling a different number of TLBs if this improves simulation performance. The simulation is architecturally-accurate, but not device-accurate. Architectural accuracy is almost always sufficient. Specify true if device accuracy is required.
l1_dcache-state_modelled, l1_icache-state_modelled, l2_cache-state_modelled
If one cache is stateful, then the others must be too.
semihosting-cmd_line
The value of argv[0] points to the first command-line argument, not to the name of an image.
vfp-enable_at_reset
This is a model-specific behavior with no hardware equivalent.

Table 3-136 Ports

Name Protocol Type Description
cfgend0 2.7.2 Signal protocol Slave Configure BE8 mode after a reset.
cfgnmfi 2.7.2 Signal protocol Slave Configure FIQs as non-maskable after a reset.
cfgte 2.7.2 Signal protocol Slave Configure exceptions to be taken in thumb mode after a reset.
clk_in ClockSignal Slave The clock signal connected to the clk_in port is used to determine the rate at which the core executes instructions.
dmaexterrirq 2.7.2 Signal protocol Master L1 PLE error interrupt.
dmairq 2.7.2 Signal protocol Master Interrupt signal from L1 PLE.
dmasirq 2.7.2 Signal protocol Master Secure interrupt signal from L1 PLE.
fiq 2.7.2 Signal protocol Slave This signal drives the CPU's fast-interrupt handling.
irq 2.7.2 Signal protocol Slave This signal drives the CPU's interrupt handling.
pmuirq 2.7.2 Signal protocol Master Interrupt signal from performance monitoring unit.
pvbus_m PVBus Master The core will generate bus requests on this port.
reset 2.7.2 Signal protocol Slave Raising this signal will put the core into reset mode.
ticks 2.6.3 InstructionCount protocol Master Port allowing the number of instructions since startup to be read from the CPU.
vinithi 2.7.2 Signal protocol Slave Configure high vectors after a reset.

Table 3-137 Parameters for ARM_Cortex-A8

Name Type Default value Description
CFGEND0 bool 0x0 Initialize to BE8 endianness
CFGNMFI bool 0x0 Enable nonmaskable FIQ interrupts on startup
CFGTE bool 0x0 Initialize to take exceptions in T32 state. Model starts in T32 state
CP15SDISABLE bool 0x0 Initialize to disable access to some CP15 registers
VINITHI bool 0x0 Initialize with high vectors enabled
cpi_div int 0x1 Divider for calculating CPI (Cycles Per Instruction)
cpi_mul int 0x1 Multiplier for calculating CPI (Cycles Per Instruction)
device-accurate-tlb bool 0x0 Specify whether all TLBs are modeled
implements_vfp bool 0x1 Set whether the model has been built with VFP and NEON support
l1_dcache-hit_latency int 0x0 L1 D-Cache timing annotation latency for hit. Intended to model the tag-lookup time. This is only used when l1_dcache-state_modelled=true.
l1_dcache-maintenance_latency int 0x0 L1 D-Cache timing annotation latency for cache maintenance operations given in total ticks. This is only used when l1_dcache-state_modelled=true.
l1_dcache-miss_latency int 0x0 L1 D-Cache timing annotation latency for miss. Intended to model the time for failed tag-lookup and allocation of intermediate buffers. This is only used when l1_dcache-state_modelled=true.
l1_dcache-read_access_latency int 0x0 L1 D-Cache timing annotation latency for read accesses given in ticks per access. If this parameter is non-zero, per-access latencies will be used instead of per-byte even if l1_dcache-read_latency is set. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus, this is only used when l1_dcache-state_modelled=true.
l1_dcache-read_latency int 0x0 L1 D-Cache timing annotation latency for read accesses given in ticks per byte accessed.l1_dcache-read_access_latency must be set to 0 for per-byte latencies to be applied. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus. This is only used when l1_dcache-state_modelled=true.
l1_dcache-size int 0x8000 Set L1 D-cache size in bytes
l1_dcache-state_modelled bool 0x0 Include Level 1 data cache state model
l1_dcache-write_access_latency int 0x0 L1 D-Cache timing annotation latency for write accesses given in ticks per access. If this parameter is non-zero, per-access latencies will be used instead of per-byte even if l1_dcache-write_latency is set. This is only used when l1_dcache-state_modelled=true.
l1_dcache-write_latency int 0x0 L1 D-Cache timing annotation latency for write accesses given in ticks per byte accessed. l1_dcache-write_access_latency must be set to 0 for per-byte latencies to be applied. This is only used when l1_dcache-state_modelled=true.
l1_icache-hit_latency int 0x0 L1 I-Cache timing annotation latency for hit. Intended to model the tag-lookup time. This is only used when l1_icache-state_modelled=true.
l1_icache-miss_latency int 0x0 L1 I-Cache timing annotation latency for miss. Intended to model the time for failed tag-lookup and allocation of intermediate buffers. This is only used when l1_icache-state_modelled=true.
l1_icache-read_access_latency int 0x0 L1 I-Cache timing annotation latency for read accesses given in ticks per access. If this parameter is non-zero, per-access latencies will be used instead of per-byte even if l1_icache-read_latency is set. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus, this is only used when l1_icache-state_modelled=true.
l1_icache-read_latency int 0x0 L1 I-Cache timing annotation latency for read accesses given in ticks per byte accessed.l1_icache-read_access_latency must be set to 0 for per-byte latencies to be applied. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus. This is only used when l1_icache-state_modelled=true.
l1_icache-size int 0x8000 Set L1 I-cache size in bytes
l1_icache-state_modelled bool 0x0 Include Level 1 instruction cache state model
l2_cache-hit_latency int 0x0 L2 Cache timing annotation latency for hit. Intended to model the tag-lookup time. This is only used when l2_cache-state_modelled=true.
l2_cache-maintenance_latency int 0x0 L2 Cache timing annotation latency for cache maintenance operations given in total ticks. This is only used when l2_cache-state_modelled=true.
l2_cache-miss_latency int 0x0 L2 Cache timing annotation latency for miss. Intended to model the time for failed tag-lookup and allocation of intermediate buffers. This is only used when l2_cache-state_modelled=true.
l2_cache-read_access_latency int 0x0 L2 Cache timing annotation latency for read accesses given in ticks per access. If this parameter is non-zero, per-access latencies will be used instead of per-byte even if l2_cache-read_latency is set. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus, this is only used when l2_cache-state_modelled=true.
l2_cache-read_latency int 0x0 L2 Cache timing annotation latency for read accesses given in ticks per byte accessed.l2_cache-read_access_latency must be set to 0 for per-byte latencies to be applied. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus. This is only used when l2_cache-state_modelled=true.
l2_cache-size int 0x40000 Set L2 cache size in bytes
l2_cache-snoop_data_transfer_latency int 0x0 L2 Cache timing annotation latency for received snoop accesses that perform a data transfer given in ticks per byte accessed. This is only used when l2_cache-state_modelled=true.
l2_cache-state_modelled bool 0x0 Include unified Level 2 cache state model
l2_cache-write_access_latency int 0x0 L2 Cache timing annotation latency for write accesses given in ticks per access. If this parameter is non-zero, per-access latencies will be used instead of per-byte even if l2_cache-write_latency is set. This is only used when l2_cache-state_modelled=true.
l2_cache-write_latency int 0x0 L2 Cache timing annotation latency for write accesses given in ticks per byte accessed. l2_cache-write_access_latency must be set to 0 for per-byte latencies to be applied. This is only used when l2_cache-state_modelled=true.
master_id int 0x0 Master ID presented in bus transactions
min_sync_level int 0x0 Force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
semihosting-ARM_HLT int 0xf000 ARM HLT number for semihosting
semihosting-ARM_SVC int 0x123456 ARM SVC number for semihosting
semihosting-Thumb_HLT int 0x3c Thumb HLT number for semihosting
semihosting-Thumb_SVC int 0xab Thumb SVC number for semihosting
semihosting-cmd_line string "" Command line available to semihosting SVC calls
semihosting-cwd string "" Base directory for semihosting file access.
semihosting-enable bool 0x1 Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false
semihosting-heap_base int 0x0 Virtual address of heap base
semihosting-heap_limit int 0xf000000 Virtual address of top of heap
semihosting-hlt-enable bool 0x0 Enable semihosting HLT traps. Applications that use HLT semihosting must set this parameter to true and the semihosting-enable parameter to true
semihosting-stack_base int 0x10000000 Virtual address of base of descending stack
semihosting-stack_limit int 0xf000000 Virtual address of stack limit
siliconID int 0x41000000 Value as read by the system coprocessor siliconID register
vfp-enable_at_reset bool 0x0 Enable coprocessor access and VFP at reset
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