3.4.32 ARMCortexM23CT

ARMCortexM23CT CPU component. This model is written in C++.

ARMCortexM23CT contains the following CADI targets:

  • ARM_Cortex-M23

ARMCortexM23CT contains the following MTI components:

Differences between the CT model and RTL implementations

The model does not support MTB, ETM, or TPIU. MTB RAM is absent on the model.

Table 3-156 Ports

Name Protocol Type Description
ahbd PVBus Slave Debug AHB - core bus slave driven by the DAP.
bigend Signal Slave Configure big endian data format.
clk_in ClockSignal Slave The clock signal connected to the clk_in port is used to determine the rate at which the core executes instructions.
cpuwait Signal Slave Clear = Core goes through reset sequence as normal, Set = Core waits out of reset.
currpri Value Master Current execution priority.
dap_s PVBus Slave Debug Access Port (DAP).
dbgen Signal Slave Invasive debug control signals. Debug enable, Set=enabled, Clear=disabled
dbgrestart Signal Slave External request to leave debug state
dbgrestarted Signal Master Acknowledge for DBGRESTART
edbgrq Signal Slave External debug request.
event Signal Peer This peer port of event input (and output) is for wakeup from WFE and corresponds to the RTL TXEV and RXEV signals.
halted Signal Master Core is in halt mode debug state
hreset Signal Slave Raising this signal will put the core into reset mode (but does not reset the debug logic).
idau PVBus Master The core will generate IDAU requests on this port.
idau_invalidate_region Value_64 Slave 64 bit number to invalid IDAU memory ranage (start_address<<32|end_address)
initvtor Value Slave Reset configuration port - Secure Vector table offset (VTOR.TBLOFF[31:7]) out of reset This port remains functional no matter ARMv8-M Security Extensions are included or not When ARMv8-M Security Extensions are not included, all exceptions will use NS vector base address given by this port.
initvtorns Value Slave Reset configuration port - Non-Secure Vector table offset (VTOR.TBLOFF[31:7]) out of reset It becomes functional when ARMv8-M Security Extensions are included When ARMv8-M Security Extensions are not included, this port will be ignored.
io_port_in PVBus Slave I/O port pair. See the documentation for the io_port_out port.
io_port_out PVBus Master I/O port pair. Used if IOP is true. Transactions from io_port_out which do not "match" should be returned via io_port_in. For performance reasons, the I/O port interface is not modelled directly. Instead, a simple PVBus gasket is inserted at the point in the memory system where the I/O port would be. In hardware, a device would be attached to the port which would tell the CPU whether it would like to intercept each transaction, given its address. This can be modelled in a performant manner by connecting a PVBusMapper-based device to io_port_out which intercepts transactions of interest and passes other transactions back to the CPU via io_port_in. Your I/O port device model is also responsible for aborting transactions which would be aborted on hardware (e.g. exclusives) if necessary.
irq[240] Signal Slave This signal array delivers signals to the NVIC.
lockup Signal Master Asserted when the processor is in lockup state.
niden Signal Slave Non-invasive debug enable, Set=enabled, Clear=disabled
nmi Signal Slave Configure non maskable interrupt.
poreset Signal Slave Raising this signal will do a power-on reset of the core.
pv_ppbus_m PVBus Master The core will generate External Private Peripheral Bus requests on this port.
pvbus_m PVBus Master The core will generate bus requests on this port.
sleepdeep Signal Master Asserted when the processor is in deep sleep.
sleeping Signal Master Asserted when the processor is in sleep.
spiden Signal Slave Secure Debug enable , Set=enabled, Clear=disabled
spniden Signal Slave Secure Non-invasive debug enable, Set=enabled, Clear=disabled
stcalib Value Slave This is the calibration value for the Secure (or only, when ARMv8-M Security Extensions are not included) SysTick timer.
stcalibns Value Slave This is the calibration value for the Non-Secure SysTick timer. When ARMv8-M Security Extensions are not included, this port will be ignored.
stclk ClockSignal Slave This is the reference clock for the SysTick timer.
sysresetreq Signal Master Asserted to indicate that a reset is required.
ticks InstructionCount Master Port allowing the number of instructions since startup to be read from the CPU.

Table 3-157 Parameters for ARM_Cortex-M23

Name Type Default value Description
BE bool 0x0 Initialize processor to big endian mode
BKPT int 0x4 Number of breakpoint unit comparators implemented
DBG bool 0x1 Set whether debug extensions are implemented
INITVTOR int 0x0 Secure vector-table offset at reset
INITVTORNS int 0x0 Non-Secure vector-table offset at reset
IOP bool 0x0 Send all d-side transactions to the port, io_port_out. Transactions which do not match should be returned to the port, io_port_in
IRQDIS0 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+0]
IRQDIS1 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+32]
IRQDIS2 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+64]
IRQDIS3 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+96]
IRQDIS4 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+128]
IRQDIS5 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+160]
IRQDIS6 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+192]
IRQDIS7 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+224]
MPU_NS int 0x8 Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions
MPU_S int 0x8 Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored
NUMIRQ int 0x10 Number of user interrupts
SAU int 0x4 Number of SAU regions (0 => no SAU)
SAU_CTRL.ALLNS bool 0x0 At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set
SAU_CTRL.ENABLE bool 0x0 Enable SAU at reset
SAU_REGION0.BADDR int 0x0 Base address of SAU region0 at reset
SAU_REGION0.ENABLE bool 0x0 Enable SAU region0 at reset
SAU_REGION0.LADDR int 0x0 Limit address of SAU region0 at reset
SAU_REGION0.NSC bool 0x0 Set NSC for SAU region0 at reset
SAU_REGION1.BADDR int 0x0 Base address of SAU region1 at reset
SAU_REGION1.ENABLE bool 0x0 Enable SAU region1 at reset
SAU_REGION1.LADDR int 0x0 Limit address of SAU region1 at reset
SAU_REGION1.NSC bool 0x0 Set NSC for SAU region1 at reset
SAU_REGION2.BADDR int 0x0 Base address of SAU region2 at reset
SAU_REGION2.ENABLE bool 0x0 Enable SAU region2 at reset
SAU_REGION2.LADDR int 0x0 Limit address of SAU region2 at reset
SAU_REGION2.NSC bool 0x0 Set NSC for SAU region2 at reset
SAU_REGION3.BADDR int 0x0 Base address of SAU region3 at reset
SAU_REGION3.ENABLE bool 0x0 Enable SAU region3 at reset
SAU_REGION3.LADDR int 0x0 Limit address of SAU region3 at reset
SAU_REGION3.NSC bool 0x0 Set NSC for SAU region3 at reset
SAU_REGION4.BADDR int 0x0 Base address of SAU region4 at reset
SAU_REGION4.ENABLE bool 0x0 Enable SAU region4 at reset
SAU_REGION4.LADDR int 0x0 Limit address of SAU region4 at reset
SAU_REGION4.NSC bool 0x0 Set NSC for SAU region4 at reset
SAU_REGION5.BADDR int 0x0 Base address of SAU region5 at reset
SAU_REGION5.ENABLE bool 0x0 Enable SAU region5 at reset
SAU_REGION5.LADDR int 0x0 Limit address of SAU region5 at reset
SAU_REGION5.NSC bool 0x0 Set NSC for SAU region5 at reset
SAU_REGION6.BADDR int 0x0 Base address of SAU region6 at reset
SAU_REGION6.ENABLE bool 0x0 Enable SAU region6 at reset
SAU_REGION6.LADDR int 0x0 Limit address of SAU region6 at reset
SAU_REGION6.NSC bool 0x0 Set NSC for SAU region6 at reset
SAU_REGION7.BADDR int 0x0 Base address of SAU region7 at reset
SAU_REGION7.ENABLE bool 0x0 Enable SAU region7 at reset
SAU_REGION7.LADDR int 0x0 Limit address of SAU region7 at reset
SAU_REGION7.NSC bool 0x0 Set NSC for SAU region7 at reset
SECEXT bool 0x1 Whether the ARMv8-M Security Extensions are included
SYST int 0x2 Include SysTick timer functionality (0=Absent, 1=Secure only, 2=Secure and NS)
VTOR bool 0x1 Include Vector Table Offset Register
WIC bool 0x1 Include support for WIC-mode deep sleep
WPT int 0x4 Number of watchpoint unit comparators implemented
cpi_div int 0x1 divider for calculating CPI (Cycles Per Instruction)
cpi_mul int 0x1 multiplier for calculating CPI (Cycles Per Instruction)
ignore-SCR.SLEEPONEXIT bool 0x0 Never sleep on exit from handler to thread mode.
master_id int 0x0 Master ID presented in bus transactions
min_sync_level int 0x0 force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
scheduler_mode int 0x0 Control the interleaving of instructions in this processor (0=default long quantum, 1=low latency mode, short quantum and signal checking, 2=lock-breaking mode, long quantum with additional context switches near load-exclusive instructions, 3=ISSCompare)
semihosting-Thumb_SVC int 0xab T32 SVC number for semihosting
semihosting-cmd_line string "" Command line available to semihosting SVC calls
semihosting-cwd string "" Base directory for semihosting file access.
semihosting-enable bool 0x1 Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
semihosting-heap_base int 0x0 Virtual address of heap base
semihosting-heap_limit int 0x10700000 Virtual address of top of heap
semihosting-prefix bool 0x0 Prefix semihosting output with target instance name
semihosting-stack_base int 0x10700000 Virtual address of base of descending stack
semihosting-stack_limit int 0x10800000 Virtual address of stack limit
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