3.4.27 ARMCortexM0CT

ARMCortexM0CT CPU component. This model is written in C++ and models version r0p0 of the RTL.

ARMCortexM0CT contains the following CADI targets:

  • ARM_Cortex-M0

ARMCortexM0CT contains the following MTI components:

Differences between the CT model and RTL implementations

This model does not have a parameter that is equivalent to the RAR integration option. The architecturally required register state is reset.

ARM does not guarantee that all ARMv7-M behavior is absent from models of ARMv6-M cores. As a consequence, ARM does not guarantee that code that runs on ARMv7-M cores but fails on ARMv6-M cores also fails on ARMv6-M Fast Models cores.

This model exposes, through CADI, a VTOR register, but this register in not present in hardware.

Table 3-143 Ports

Name Protocol Type Description
ahbd PVBus Slave Debug AHB - core bus slave driven by the DAP.
bigend Signal Slave Configure big endian data format.
clk_in ClockSignal Slave The clock signal connected to the clk_in port is used to determine the rate at which the core executes instructions.
currpri Value Master Current execution priority.
edbgrq Signal Slave External debug request.
event Signal Peer This peer port of event input (and output) is for wakeup from WFE and corresponds to the RTL TXEV and RXEV signals.
intisr[32] Signal Slave This signal array delivers signals to the NVIC.
intnmi Signal Slave Configure non maskable interrupt.
lockup Signal Master Asserted when the processor is in lockup state.
poreset Signal Slave Raising this signal will do a power-on reset of the core.
pv_ppbus_m PVBus Master The core will generate External Private Peripheral Bus requests on this port.
pvbus_m PVBus Master The core will generate bus requests on this port.
sleepdeep Signal Master Asserted when the processor is in deep sleep.
sleeping Signal Master Asserted when the processor is in sleep.
stcalib Value Slave This is the calibration value for the SysTick timer.
stclk ClockSignal Slave This is the reference clock for the SysTick timer.
sysreset Signal Slave Raising this signal will put the core into reset mode (but does not reset the debug logic).
sysresetreq Signal Master Asserted to indicate that a reset is required.
ticks InstructionCount Master Port allowing the number of instructions since startup to be read from the CPU.

Table 3-144 Parameters for ARM_Cortex-M0

Name Type Default value Description
BIGENDINIT bool 0x0 Initialize processor to big endian mode
BKPT int 0x4 Number of breakpoint unit comparators implemented
DBG bool 0x1 Set whether debug extensions are implemented
NUM_IRQ int 0x20 Number of user interrupts
SYST bool 0x1 Enable support for SysTick timer functionality
WIC bool 0x1 Include support for WIC-mode deep sleep
WPT int 0x2 Number of watchpoint unit comparators implemented
cpi_div int 0x1 divider for calculating CPI (Cycles Per Instruction)
cpi_mul int 0x1 multiplier for calculating CPI (Cycles Per Instruction)
master_id int 0x0 Master ID presented in bus transactions
min_sync_level int 0x0 force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
semihosting-Thumb_SVC int 0xab T32 SVC number for semihosting
semihosting-cmd_line string "" Command line available to semihosting SVC calls
semihosting-cwd string "" Base directory for semihosting file access.
semihosting-enable bool 0x1 Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
semihosting-heap_base int 0x0 Virtual address of heap base
semihosting-heap_limit int 0x10700000 Virtual address of top of heap
semihosting-prefix bool 0x0 Prefix semihosting output with target instance name
semihosting-stack_base int 0x10700000 Virtual address of base of descending stack
semihosting-stack_limit int 0x10800000 Virtual address of stack limit
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