3.4.35 ARMCortexR4CT

ARMCortexR4CT CPU component. This model is written in C++ and models version r1p2 of the RTL.

ARMCortexR4CT contains the following CADI targets:

  • ARM_Cortex-R4
  • PVCache

ARMCortexR4CT contains the following MTI components:

Differences between the CT model and RTL implementations

This component has the following differences from the corresponding revision of the RTL implementation:

  • There is a single memory port combining instruction, data, DMA and peripheral access.
  • ECC and parity schemes are not supported (although the registers might be present).
  • The dual core redundancy configuration is not supported.
  • TCMs are modeled internally and the model does not support external TCMs or the ports associated with them.
  • The hardware refers to the TCMs as "A" and "B". The model refers to these as "i" and "d".
  • The RTL permits two data TCMs, B0 and B1, to be configured for extra bandwidth. These are not modeled.

Caches

This PV model does not model Level 1 or Level 2 caches. The system coprocessor registers related to cache operations permit cache-aware software to work, but in most cases they only check register access permissions:

  • Invalidate and/or Clean Entire ICache/DCache.
  • Invalidate and/or Clean ICache/DCache by MVA.
  • Invalidate and/or Clean ICache/DCache by Index.
  • Invalidate and/or Clean Both Caches.
  • Cache Dirty Status.
  • Data Write Barrier.
  • Data Memory Barrier.
  • Prefetch ICache Line.
  • ICache/DCache lockdown.
  • ICache/DCache master valid.
  • Cache Size Override.
  • Validation registers.

Debug features

All core and implemented registers are visible in the debugger. The CP14 DSCR register is visible for compatibility with some debuggers. This register has no defined behavior.

This component directly supports single address unconditional instruction breakpoints, unconditional instruction address range breakpoints, and single address unconditional data breakpoints.

The debugger might augment these with more complex combinations of breakpoints.

The model does not support CADI exception breakpoints. Instead, it implements exception breakpoints as register breakpoints on pseudoregisters, named after the exceptions, in the Vectors register group.

This component presents one 4GB view of virtual memory.

Additional port and parameter information

cfgie
The model implements this port, although it is optional in hardware.
pvbus_s
Slave port to access the TCM RAM. Bits [3:0] of the user flags in the transaction are used to select the TCM:
  • 1 selects the ATCM.
  • 2 selects the BTCM.
  • Any other value is reserved.
semihosting-cmd_line
The value of argv[0] points to the first command-line argument, not to the name of an image.
vfp-enable_at_reset
This is a model-specific behavior with no hardware equivalent.

Table 3-164 Ports

Name Protocol Type Description
cfgend0 Signal Slave Configure BE8 mode after a reset.
cfgie Signal Slave Configure big endian instruction format after a reset.
cfgnmfi Signal Slave Configure FIQs as non-maskable after a reset.
cfgte Signal Slave Configure exceptions to be taken in thumb mode after a reset.
clk_in ClockSignal Slave The clock signal connected to the clk_in port is used to determine the rate at which the core executes instructions.
cpuhalt Signal Slave Raising this signal will put the core into halt mode.
fiq Signal Slave This signal drives the CPU's fast-interrupt handling.
initramd Signal Slave Configure DTCM enabled after a reset.
initrami Signal Slave Configure ITCM enabled after a reset.
irq Signal Slave This signal drives the CPU's interrupt handling.
loczrama Signal Slave Location of ATCM at reset.
pmuirq Signal Master Interrupt signal from performance monitoring unit.
pvbus_m PVBus Master The core will generate bus requests on this port.
pvbus_s PVBus Slave Slave access to TCMs.
reset Signal Slave Raising this signal will put the core into reset mode.
standbywfi Signal Master Signal from the core that it is waiting in standby for an interrupt.
ticks InstructionCount Master Port allowing the number of instructions since startup to be read from the CPU.
vic_ack Signal Master Vic acknowledge port to primary VIC.
vic_addr Value Slave Vic address port from primary VIC.
vinithi Signal Slave Configure high vectors after a reset.

Table 3-165 Parameters for ARM_Cortex-R4

Name Type Default value Description
CFGEND0 bool 0x0 Initialize to BE8 endianness
CFGIE bool 0x0 Set the reset value of the instruction endian bit
CFGNMFI bool 0x0 Enable nonmaskable FIQ interrupts on startup
CFGTE bool 0x0 Initialize to take exceptions in T32 state. Model starts in T32 state
INITRAMD bool 0x0 Set or reset the INITRAMD signal
INITRAMI bool 0x0 Set or reset the INITRAMI signal
LOCZRAMI bool 0x0 Set or reset the LOCZRAMI signal
NUM_MPU_REGION int 0x8 Number of MPU regions
VINITHI bool 0x0 Initialize with high vectors enabled
cpi_div int 0x1 Divider for calculating CPI (Cycles Per Instruction)
cpi_mul int 0x1 Multiplier for calculating CPI (Cycles Per Instruction)
dcache-size int 0x10000 Set D-cache size in bytes
dcache-state_modelled bool 0x0 Set whether D-cache has stateful implementation
dtcm0_base int 0x800000 Base address of DTCM at startup
dtcm0_size int 0x8 Size of DTCM in KB
icache-size int 0x10000 Set I-cache size in bytes
icache-state_modelled bool 0x0 Set whether I-cache has stateful implementation
implements_vfp bool 0x1 Set whether the model has been built with VFP support
itcm0_base int 0x0 Base address of ITCM at startup
itcm0_size int 0x8 Size of ITCM in KB
master_id int 0x0 Master ID presented in bus transactions
min_sync_level int 0x0 force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
semihosting-ARM_HLT int 0xf000 ARM HLT number for semihosting
semihosting-ARM_SVC int 0x123456 ARM SVC number for semihosting
semihosting-Thumb_HLT int 0x3c Thumb HLT number for semihosting
semihosting-Thumb_SVC int 0xab Thumb SVC number for semihosting
semihosting-cmd_line string "" Command line available to semihosting SVC calls
semihosting-cwd string "" Base directory for semihosting file access.
semihosting-enable bool 0x1 Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false
semihosting-heap_base int 0x0 Virtual address of heap base
semihosting-heap_limit int 0xf000000 Virtual address of top of heap
semihosting-hlt-enable bool 0x0 Enable semihosting HLT traps. Applications that use HLT semihosting must set this parameter to true and the semihosting-enable parameter to true
semihosting-stack_base int 0x10000000 Virtual address of base of descending stack
semihosting-stack_limit int 0xf000000 Virtual address of stack limit
vfp-enable_at_reset bool 0x0 Enable coprocessor access and VFP at reset
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