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A PVBusSlave handles incoming transactions, and handles support for mapping regions of device address space to work as RAM/ROM/device memory. This model is written in C++.
PVBusSlave contains the following MTI components:
Any component that acts as a bus slave must:
By default, the PVBusSlave translates all transactions into
write() requests on the device port.
The control port enables you to configure the PVBusSlave for a device. This lets you define the behavior of the different regions of the address space on the device. You can configure regions separately for read and write, at a 4KB granularity. This permits you to set memory-like, device-like, abort, or ignore access address regions.
Transactions to memory-like regions are handled internally by the PVBusSlave subcomponent. Abort and ignore regions are also handled by the PVBusSlave.
Transactions to device-like regions are forwarded to the device port. Your device must implement the
write() methods on the device port if any regions are configured as device-like.
This component typically does not significantly affect the performance of a PV system. However, correct implementation of the PVBusSlave component is critical to the performance of the overall PV system. For example, routing a request to a PVDevice port is slower than letting the PVBusSlave component handle the request internally. ARM recommends using the internal support for memory-like regions where possible.
The values assigned to
pv::accessMode control what happens when an address is accessed. Legal values for the enumeration are:
deviceport, where the necessary behavior can be implemented by the component.
Table 3-50 Ports
||Slave||Enables the owning component to control which regions of the device memory are to be handled as RAM/ROM/Device. These settings can be changed dynamically. For example, when a Flash component is being programmed, it can switch to treating reads as Device requests instead of ROM requests.|
||Master||Passes on requests for peripheral register accesses to permit the owning component to handle the request.|
||Slave||Handles incoming requests from bus masters.|
||Slave||On the assert of this signal, a reset of the bus slave will be latched this is used by the bus deadlock detection logic.|