3.10.25 GICv3IRI_Filter

GICv3 metacomponent for redistribution of interrupts( contains Distributor, and configurable numbers of ITSs and Redistributors. Validation only version. This model is written in C++.

GICv3IRI_Filter contains the following CADI targets:

  • GICv3IRI

GICv3IRI_Filter contains the following MTI components:

GICv3IRI_Filter - about

The GICv3IRI_Filter has similar behavior to the GICv3IRI, except for the slave interface. Any transaction accessing a 4KB page that is not used by the GIC, as configurable through the parameters, is forwarded to the pvbus_filtermiss_m port, which is only present in this variant.

Additional parameter information

GICD_ITARGETSR-RAZWI
Legacy routing, GICv2-style, fixes interrupts to target the first processor in the system.

Table 3-326 Ports

Name Protocol Type Description
cfgsdisable Signal Slave Disable some SPIs signal.
extended_ppi_in_n[64] Signal Slave Extended private peripheral interrupts (ID1056-ID1119) for cpu n, where n is in the range 0-255.
extended_spi_in[1024] Signal Slave Extended Shared peripheral interrupts.
po_reset Signal Slave Resets.
ppi_in_n[16] Signal Slave Private peripheral interrupts (ID16-ID31) for cpu n, where n is in the range 0-255.
pvbus_filtermiss_m PVBus Master Passthrough for accesses to pages not used by the GIC IRI.
pvbus_m PVBus Master Memory bus for transactions generated by the GIC.
pvbus_s PVBus Slave Memory bus in.
redistributor_m[256] GICv3Comms Master Input from and output to CPU interface.
reset Signal Slave Resets.
spi_in[988] Signal Slave Shared peripheral interrupts.
wake_request[256] Signal Master Power management outputs.
wire_to_msi_0[1024] Signal Slave Wire-to-MSI interrupts for architectural consolidator 0.
wire_to_msi_1[1024] Signal Slave Wire-to-MSI interrupts for architectural consolidator 1.
wire_to_msi_2[1024] Signal Slave Wire-to-MSI interrupts for architectural consolidator 2.
wire_to_msi_3[1024] Signal Slave Wire-to-MSI interrupts for architectural consolidator 3.

Table 3-327 Parameters for GICv3IRI

Name Type Default value Description
A3-affinity-supported bool 0x0 Device supports affinity level 3 values that are non-zero.
ARE-fixed-to-one bool 0x0 GICv2 compatibility is not supported and GICD_CTLR.ARE_* is always one
CPU-affinities string "" A comma separated list of dotted quads containing the affinities of all PEs connected to this IRI. If CPU-affinities-file is specified, this parameter is ignored.
CPU-affinities-file string "" A file containing comma separated list of dotted quads containing the affinities of all PEs connected to this IRI. If this parameter is specified, CPU-affinities parameter will be ignored even when it is given.
DPG-ARE-only bool 0x0 Limit application of DPG bits to interrupt groups for which ARE=1
DPG-bits-implemented bool 0x0 Enable implementation of interrupt group participation bits or DPG bits in GICR_CTLR
DS-fixed-to-zero bool 0x0 Enable/disable support of single security state
GICD-alias int 0x0 In GICv2 mode: the base address for a 4k page alias of the first 4k of the Distributor page, in GICv3 mode. the base address of a 64KB page containing message based SPI signalling register aliases(0:Disabled)
GICD-legacy-registers-as-reserved bool 0x0 When ARE is RAO/WI, makes superfluous registers in GICD reserved ( including for the purpose of STATUSR updates)
GICD_ITARGETSR-RAZWI bool 0x0 If true, the GICD_ITARGETS registers are RAZ/WI
GICD_PIDR int 0x0 The value for the GICD_PIDR registers, if non-zero. Note: fixed fields (device type etc.) will be overriden in this value.
GICR_PIDR int 0x0 The value for the GICR_PIDR registers, if non-zero. Note: fixed fields (device type etc.) will be overriden in this value.
GICR_PROPBASER-read-only bool 0x0 GICR_PROPBASER register is read-only.
GICR_PROPBASER-reset-value int 0x0 Value of GICR_PROPBASER on reset.
GITS_BASER0-entry-bytes int 0x8 Number of bytes required per entry for GITS_BASER0 register.
GITS_BASER0-indirect-RAZ bool 0x0 Indirect field for GITS_BASER0 register is RAZ/WI.
GITS_BASER0-type int 0x0 Type field for GITS_BASER0 register. 0 = Unimplemented; 1 = Devices; 2 = Virtual Processors; 3 = Physical Processors; 4 = Collections
GITS_BASER1-entry-bytes int 0x8 Number of bytes required per entry for GITS_BASER1 register.
GITS_BASER1-indirect-RAZ bool 0x0 Indirect field for GITS_BASER1 register is RAZ/WI.
GITS_BASER1-type int 0x0 Type field for GITS_BASER1 register. 0 = Unimplemented; 1 = Devices; 2 = Virtual Processors; 3 = Physical Processors; 4 = Collections
GITS_BASER2-entry-bytes int 0x8 Number of bytes required per entry for GITS_BASER2 register.
GITS_BASER2-indirect-RAZ bool 0x0 Indirect field for GITS_BASER2 register is RAZ/WI.
GITS_BASER2-type int 0x0 Type field for GITS_BASER2 register. 0 = Unimplemented; 1 = Devices; 2 = Virtual Processors; 3 = Physical Processors; 4 = Collections
GITS_BASER3-entry-bytes int 0x8 Number of bytes required per entry for GITS_BASER3 register.
GITS_BASER3-indirect-RAZ bool 0x0 Indirect field for GITS_BASER3 register is RAZ/WI.
GITS_BASER3-type int 0x0 Type field for GITS_BASER3 register. 0 = Unimplemented; 1 = Devices; 2 = Virtual Processors; 3 = Physical Processors; 4 = Collections
GITS_BASER4-entry-bytes int 0x8 Number of bytes required per entry for GITS_BASER4 register.
GITS_BASER4-indirect-RAZ bool 0x0 Indirect field for GITS_BASER4 register is RAZ/WI.
GITS_BASER4-type int 0x0 Type field for GITS_BASER4 register. 0 = Unimplemented; 1 = Devices; 2 = Virtual Processors; 3 = Physical Processors; 4 = Collections
GITS_BASER5-entry-bytes int 0x8 Number of bytes required per entry for GITS_BASER5 register.
GITS_BASER5-indirect-RAZ bool 0x0 Indirect field for GITS_BASER5 register is RAZ/WI.
GITS_BASER5-type int 0x0 Type field for GITS_BASER5 register. 0 = Unimplemented; 1 = Devices; 2 = Virtual Processors; 3 = Physical Processors; 4 = Collections
GITS_BASER6-entry-bytes int 0x8 Number of bytes required per entry for GITS_BASER6 register.
GITS_BASER6-indirect-RAZ bool 0x0 Indirect field for GITS_BASER6 register is RAZ/WI.
GITS_BASER6-type int 0x0 Type field for GITS_BASER6 register. 0 = Unimplemented; 1 = Devices; 2 = Virtual Processors; 3 = Physical Processors; 4 = Collections
GITS_BASER7-entry-bytes int 0x8 Number of bytes required per entry for GITS_BASER7 register.
GITS_BASER7-indirect-RAZ bool 0x0 Indirect field for GITS_BASER7 register is RAZ/WI.
GITS_BASER7-type int 0x0 Type field for GITS_BASER7 register. 0 = Unimplemented; 1 = Devices; 2 = Virtual Processors; 3 = Physical Processors; 4 = Collections
GITS_PIDR int 0x0 The value for the GITS_PIDR registers, if non-zero. Note: fixed fields (device type etc.) will be overriden in this value.
ICFGR-PPI-mask int 0xaaaaaaaa Mask for writes to ICFGR registers that configure PPIs
ICFGR-PPI-reset int 0x0 Reset value for ICFGR regesters that configure PPIs
ICFGR-SGI-mask int 0x0 Mask for writes to ICFGR registers that configure SGIs
ICFGR-SGI-reset int 0xaaaaaaaa Reset value for ICFGR registers that configure SGIs
ICFGR-SPI-mask int 0xaaaaaaaa Mask for writes to ICFGR registers that configure SPIs
ICFGR-SPI-reset int 0x0 Reset value for ICFGR regesters that configure SPIs
ICFGR-rsvd-bit bool 0x0 If ARE=0, the value of reserved bits i.e. bit 0,2,4..30 of ICFGRn for n>0
IGROUP-PPI-mask int 0xffff Mask for writes to PPI bits in IGROUP registers
IGROUP-PPI-reset int 0x0 Reset value for SGI bits in IGROUP registers
IGROUP-SGI-mask int 0xffff Mask for writes to SGI bits in IGROUP registers
IGROUP-SGI-reset int 0x0 Reset value for SGI bits in IGROUP registers
IIDR int 0x0 GICD_IIDR and GICR_IIDR value
IRI-ID-bits int 0x10 Number of bits used to represent interrupts IDs in the Distributor and Redistributors, forced to 10 if LPIs are not supported
IROUTER-IRM-RAZ-WI bool 0x0 GICD_IROUTERn.InterruptRoutingMode is RAZ/WI
ITS-BASER-force-page-alignement bool 0x1 Force alignement of address writen to a GITS_BASER register to the page size configured
ITS-ID-bits int 0x10 Number of interrupt bits supported by ITS.
ITS-MOVALL-update-collections bool 0x0 Whether MOVALL command updates the collection entires
ITS-TRANSLATE64R bool 0x0 Add an implementation specific register at 0x10008 supporting 64 bit TRANSLATER (dev[63:32], interupt[31:0])
ITS-collection-ID-bits int 0x0 Number of collection bits supported by ITS (optional parameter, 0 => 16bits support and GITS_TYPER.CIL=0
ITS-count int 0x0 Number of Interrupt Translation Services to be instantiated (0=none)
ITS-cumulative-collection-tables bool 0x1 When true, the supported amount of collections is the sum of GITS_TYPER.HCC and the number of collections supported in memory, otherwise, simply the number supported in memory only. Irrelevant when HCC=0
ITS-device-bits int 0x10 Number of bits supported for ITS device IDs.
ITS-entry-size int 0x8 Number of bytes required to store each entry in the ITT tables.
ITS-hardware-collection-count int 0x0 Number of hardware collections held exclusively in the ITS
ITS-legacy-iidr-typer-offset bool 0x0 Put the GITS_IIDR and GITS_TYPER registers at their older offset of 0x8 and 0x4 respectively
ITS-shared-vPE-table int 0x0 Number of affinity levels to which the vPE configuration table is shared. This parameter is valid when has-gicv4.1 is true.
ITS-threaded-command-queue bool 0x1 Enable execution of ITS commands in a separate thread which is sometimes required for cosimulation
ITS-use-physical-target-addresses bool 0x1 Use physical hardware adresses for targets in ITS commands -- must be true for distributed implementations
ITS-vmovp-bit bool 0x0 Device supports software issuing a VMOVP to only one of the ITSs that has a mapping for a vPE. The device itself ensures synchronization of the VMOVP command across all ITSs that have mapping for that vPE.
ITS0-base int 0x0 Register base address for ITS0 (automatic if 0).
ITS1-base int 0x0 Register base address for ITS1 (automatic if 0).
ITS2-base int 0x0 Register base address for ITS2 (automatic if 0).
ITS3-base int 0x0 Register base address for ITS3 (automatic if 0).
LPI-cache-check-data bool 0x0 Enable Cached LPI data against memory checking when available for cache type
LPI-cache-type int 0x1 Cache type for LPIs, 0:No caching, 1:Full caching
MSI_IIDR int 0x0 Value returned in MSI_IIDR registers.
MSI_NS-frame0-base int 0x0 If non-zero, sets the base address used for non-secure MSI frame 0 registers.
MSI_NS-frame0-max-SPI int 0x0 Maximum SPI ID supported by non-secure MSI frame 0. Set to 0 to disable frame.
MSI_NS-frame0-min-SPI int 0x0 Minimum SPI ID supported by non-secure MSI frame 0. Set to 0 to disable frame.
MSI_NS-frame1-base int 0x0 If non-zero, sets the base address used for non-secure MSI frame 1 registers.
MSI_NS-frame1-max-SPI int 0x0 Maximum SPI ID supported by non-secure MSI frame 1. Set to 0 to disable frame.
MSI_NS-frame1-min-SPI int 0x0 Minimum SPI ID supported by non-secure MSI frame 1. Set to 0 to disable frame.
MSI_NS-frame2-base int 0x0 If non-zero, sets the base address used for non-secure MSI frame 2 registers.
MSI_NS-frame2-max-SPI int 0x0 Maximum SPI ID supported by non-secure MSI frame 2. Set to 0 to disable frame.
MSI_NS-frame2-min-SPI int 0x0 Minimum SPI ID supported by non-secure MSI frame 2. Set to 0 to disable frame.
MSI_NS-frame3-base int 0x0 If non-zero, sets the base address used for non-secure MSI frame 3 registers.
MSI_NS-frame3-max-SPI int 0x0 Maximum SPI ID supported by non-secure MSI frame 3. Set to 0 to disable frame.
MSI_NS-frame3-min-SPI int 0x0 Minimum SPI ID supported by non-secure MSI frame 3. Set to 0 to disable frame.
MSI_NS-frame4-base int 0x0 If non-zero, sets the base address used for non-secure MSI frame 4 registers.
MSI_NS-frame4-max-SPI int 0x0 Maximum SPI ID supported by non-secure MSI frame 4. Set to 0 to disable frame.
MSI_NS-frame4-min-SPI int 0x0 Minimum SPI ID supported by non-secure MSI frame 4. Set to 0 to disable frame.
MSI_NS-frame5-base int 0x0 If non-zero, sets the base address used for non-secure MSI frame 5 registers.
MSI_NS-frame5-max-SPI int 0x0 Maximum SPI ID supported by non-secure MSI frame 5. Set to 0 to disable frame.
MSI_NS-frame5-min-SPI int 0x0 Minimum SPI ID supported by non-secure MSI frame 5. Set to 0 to disable frame.
MSI_NS-frame6-base int 0x0 If non-zero, sets the base address used for non-secure MSI frame 6 registers.
MSI_NS-frame6-max-SPI int 0x0 Maximum SPI ID supported by non-secure MSI frame 6. Set to 0 to disable frame.
MSI_NS-frame6-min-SPI int 0x0 Minimum SPI ID supported by non-secure MSI frame 6. Set to 0 to disable frame.
MSI_NS-frame7-base int 0x0 If non-zero, sets the base address used for non-secure MSI frame 7 registers.
MSI_NS-frame7-max-SPI int 0x0 Maximum SPI ID supported by non-secure MSI frame 7. Set to 0 to disable frame.
MSI_NS-frame7-min-SPI int 0x0 Minimum SPI ID supported by non-secure MSI frame 7. Set to 0 to disable frame.
MSI_PIDR int 0x0 The value for the MSI_PIDR registers, if non-zero and distributor supports GICv2m. Note: fixed fields (device type etc.) will be overriden in this value.
MSI_S-frame0-base int 0x0 If non-zero, sets the base address used for secure MSI frame 0 registers.
MSI_S-frame0-max-SPI int 0x0 Maximum SPI ID supported by secure MSI frame 0. Set to 0 to disable frame.
MSI_S-frame0-min-SPI int 0x0 Minimum SPI ID supported by secure MSI frame 0. Set to 0 to disable frame.
MSI_S-frame1-base int 0x0 If non-zero, sets the base address used for secure MSI frame 1 registers.
MSI_S-frame1-max-SPI int 0x0 Maximum SPI ID supported by secure MSI frame 1. Set to 0 to disable frame.
MSI_S-frame1-min-SPI int 0x0 Minimum SPI ID supported by secure MSI frame 1. Set to 0 to disable frame.
MSI_S-frame2-base int 0x0 If non-zero, sets the base address used for secure MSI frame 2 registers.
MSI_S-frame2-max-SPI int 0x0 Maximum SPI ID supported by secure MSI frame 2. Set to 0 to disable frame.
MSI_S-frame2-min-SPI int 0x0 Minimum SPI ID supported by secure MSI frame 2. Set to 0 to disable frame.
MSI_S-frame3-base int 0x0 If non-zero, sets the base address used for secure MSI frame 3 registers.
MSI_S-frame3-max-SPI int 0x0 Maximum SPI ID supported by secure MSI frame 3. Set to 0 to disable frame.
MSI_S-frame3-min-SPI int 0x0 Minimum SPI ID supported by secure MSI frame 3. Set to 0 to disable frame.
MSI_S-frame4-base int 0x0 If non-zero, sets the base address used for secure MSI frame 4 registers.
MSI_S-frame4-max-SPI int 0x0 Maximum SPI ID supported by secure MSI frame 4. Set to 0 to disable frame.
MSI_S-frame4-min-SPI int 0x0 Minimum SPI ID supported by secure MSI frame 4. Set to 0 to disable frame.
MSI_S-frame5-base int 0x0 If non-zero, sets the base address used for secure MSI frame 5 registers.
MSI_S-frame5-max-SPI int 0x0 Maximum SPI ID supported by secure MSI frame 5. Set to 0 to disable frame.
MSI_S-frame5-min-SPI int 0x0 Minimum SPI ID supported by secure MSI frame 5. Set to 0 to disable frame.
MSI_S-frame6-base int 0x0 If non-zero, sets the base address used for secure MSI frame 6 registers.
MSI_S-frame6-max-SPI int 0x0 Maximum SPI ID supported by secure MSI frame 6. Set to 0 to disable frame.
MSI_S-frame6-min-SPI int 0x0 Minimum SPI ID supported by secure MSI frame 6. Set to 0 to disable frame.
MSI_S-frame7-base int 0x0 If non-zero, sets the base address used for secure MSI frame 7 registers.
MSI_S-frame7-max-SPI int 0x0 Maximum SPI ID supported by secure MSI frame 7. Set to 0 to disable frame.
MSI_S-frame7-min-SPI int 0x0 Minimum SPI ID supported by secure MSI frame 7. Set to 0 to disable frame.
PA_SIZE int 0x30 Number of valid bits in physical address
PPI-implemented-mask int 0xffff Mask of PPIs that are implemented. One bit per PPI bit 0 == PPI 16 (first PPI). This will affect other masks.
SPI-count int 0xe0 Number of SPIs that are implemented.
SPI-message-based-support bool 0x1 Distributor supports meassage based signaling of SPI
SPI-unimplemented string "" A comma spearated list of unimplemented SPIs ranges for sparse SPI defintion(for ex: '35, 39-42, 73)'
STATUSR-implemented bool 0x1 Determines whether the GICR_STATUSR register is implemented.
allow-LPIEN-clear bool 0x0 Allow RW behaviour on GICR_CTLR.LPIEN isntead of set once
chip-id int 0x0 Chip ID when multichip operation is enabled.
common-lpi-configuration int 0x0 Describes which re-distributors share (and must be configured with the same) LPI configuration table as described in GICR_TYPER( 0:All, 1:A.x.x.x, 2:A.B.x.x, 3:A.B.C.x
common-vPE-table-affinity string "" Affinity value in the form of 'a.b.c.d' under which vPE configuration table is shared among redistributors where level to be shared is defined by ITS-shared-vPE-table. This parameter is valid when has-gicv4.1 is true.
consolidators string "" Specify consolidators' base addresses, interrupt line counts and base interrupt IDs, in the form 'baseAddr0:itlineCount0:baseINTID0, baseAddr1:itlineCount1:baseINTID1, [etc]' (eg '0x3f100000:64:4096, 0x3f200000:64:4224'). The consolidators' count is inferred from the list (maximum of 4). If not specified, the component contains no consolidators.
delay-ITS-accesses bool 0x1 Delay accesses from the ITS until GICR_SYNCR is read.
delay-redistributor-accesses bool 0x1 Delay memory accesses from the redistributor until GICR_SYNCR is read.
direct-lpi-support bool 0x0 Enable support for LPI operations through GICR registers
enable-multichip-operation bool 0x0 Enables multi-chip operation between Distributors in distributed GIC IRI
enable_protocol_checking bool 0x0 Enable/disable protocol checking at cpu interface
enabled bool 0x1 Enable GICv3 functionality; when false the component is inactive.
extended-ppi-count int 0x0 Number of extended PPI supported
extended-spi-count int 0x0 Number of extended SPI supported
fixed-routed-spis string "" Value of IROUTER[n] register in the form 'n=a.b.c.d, n=*'. The RM bit of IROUTER is 0 when n=a.b.c.d is used else 1 when n=* is used. n can be >= 32 and <= 1019
gicv2-only bool 0x0 If true, when using the GICv3 model, pretend to be a GICv2 system
has-two-security-states bool 0x1 If true, has two security states
has_VPENDBASER-dirty-flag-on-load bool 0x0 GICR_VPENDBASER.Dirty reflects transient loading state when valid=1
has_mpam bool 0x0 Enable MPAM support on ITS and RDs
ignore-generate-sgi-when-no-are bool 0x0 Ignore GenerateSGI packets coming form the CPU interface if both ARE_S and ARE_NS are 0
irouter-default-mask string "" Default Mask value for IROUTER[32..1019] register in the form 'a.b.c.d'
irouter-default-reset string "" Default Reset Value of IROUTER[32..1019] register in the form 'a.b.c.d' or *
irouter-mask-values string "" Mask Value of IROUTER[n] register in the form 'n=a.b.c.d'.n can be >= 32 and <= 1019
irouter-reset-values string "" Reset Value of IROUTER[n] register in the form 'n=a.b.c.d or n=*'.n can be >= 32 and <= 1019
legacy-sgi-enable-rao bool 0x0 Enables for SGI associated with an ARE=0 regime are RAO/WI
local-SEIs bool 0x0 Generate SEI to signal internal issues
local-VSEIs bool 0x0 Generate VSEI to signal internal issues
lockable-SPI-count int 0x0 Number of SPIs that are locked down when CFGSDISABLE signal is asserted. Only applies for GICv2.
monolithic bool 0x0 Indicate that the implementation is not distributed
mpam_max_partid int 0xffff Maximum valid PARTID
mpam_max_pmg int 0xff Maximum valid PMG
non-ARE-core-count int 0x8 Maximum number of non-ARE cores; normally used to pass the cluster-level NUM_CORES parameter to the top-level redistributor.
outer-cacheability-support bool 0x0 Allow configuration of outer cachability attributes in ITS and Redistributor
output_attributes string "ExtendedID[62:55]=MPAM_PMG, ExtendedID[54:39]=MPAM_PARTID, ExtendedID[38]=MPAM_NS" User-defined transform to be applied to bus attributes like MasterID, ExtendedID or UserFlags. Currently, only works for MPAM Attributes encoding into bus attributes.
print-memory-map bool 0x0 Print memory map to stdout
priority-bits int 0x5 Number of implemented priority bits
processor-numbers string "" Specify processor numbers (as appears in GICR_TYPER) in the form 0.0.0.0=0,0.0.0.1=1 etc.) If not specified, will number processors starting at 0.
redistributor-threaded-sync bool 0x1 Enable execution of redistributor delayed transactions in a separate thread which is sometimes required for cosimulation
reg-base int 0x2c010000 Base for decoding GICv3 registers.
reg-base-per-redistributor string "" Base address for each redistributor in the form '0.0.0.0=0x2c010000, 0.0.0.1=0x2c020000'. All redistributors must be specified and this overrides the reg-base parameter (except that reg-base will still be used for the top-level redistributor).
sgi-range-selector-support bool 0x0 Device has support for the Range Selector feature for SGI
single-set-support bool 0x0 When true, forces redistributors to recall interrupts with a clear rather than issue a second Set command
supports-shareability bool 0x1 Device supports shareability attributes on outgoing memory bus (i.e. is modelling an ACElite port rather than an AXI4 port).
trace-speculative-lpi-property-update bool 0x0 Trace LPI propery updates performed on speculative accesses (useful for debuging LPI)
virtual-lpi-support bool 0x0 GICv4 Virtual LPIs and Direct injection of Virtual LPIs supported
virtual-priority-bits int 0x5 Number of implemented virtual priority bits
wakeup-on-reset bool 0x0 Go against specification and start redistributors in woken-up state at reset. This allows software that was written for previous versions of the GICv3 specification to work correctly. This should not be used for production code or when the distributor is used separately from the core fast model.
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