3.10.4 CCI400

Cache Coherent Interconnect for AXI4 ACE. This model is written in LISA+.

CCI400 contains the following CADI targets:

  • CCI400

CCI400 contains the following MTI components:

ACE limitation

AXI Coherency Extensions (ACE) are extensions to AXI4 that support system-level cache-coherency between multiple clusters. The ACE cache models in the Cortex®‑A15 and the Cortex‑A7, and the ACE support in the CCI-400 have the limitation that they only process one transaction at a time. Normally, the simulation processes each transaction to completion before allowing any master to generate another transaction. However, in the following situation the simulation might fail. If a SystemC bus slave calls wait() while it is processing a transaction, this call might allow another master to issue another transaction that passes through the CCI-400 or the Cortex‑A15/Cortex‑A7 caches. This situation could happen if a SystemC bus master running in another thread is connected to one of the ACE-lite ports on the CCI-400.

Notes

  • If you disable the cache_state_modelled parameter, this component has negligible performance impact. If you enable cache_state_modelled, it adds significant cost to throughput for coherent transactions.

  • This model implements the slave interface Shareable Override Register, which can be read and written, but it has no functionality.

Table 3-286 Ports

Name Protocol Type Description
acchannelen Value Slave For each upstream port, determine if it is enabled or not with respect to snoop requests.
barrierterminate Value Slave For each downstream port, determine if barriers are terminated at that port.
broadcastcachemain Value Slave For each downstream port, determine if broadcast cache maintenance operations are forwarded down that port. A three bit signal but as the model only have a single downstream port, setting any of the bits will make it work.
bufferableoverride Value Slave For each downstream port, determine if all transactions are forced to non-bufferable (AWCACHE[0] is forced to 0).
errorirq Signal Master A signal stating that the imprecise error register is nonzero.
evntcntoverflow[5] Signal Master When an event counter overflows, it sets the corresponding signal.
lint_ace_3_reset_state Signal Slave This port can be connected to the reset signals of the system attached to the pvbus_s_ace_3 port.
lint_ace_4_reset_state Signal Slave This port can be connected to the reset signals of the system attached to the pvbus_s_ace_4 port.
periphbase Value_64 Slave This port sets the base address of the private peripheral region.
pvbus_m PVBus Master Master port for all downstream memory accesses.
pvbus_s_ace_3 PVBus Slave ACE-capable slave ports.
pvbus_s_ace_4 PVBus Slave ACE-capable slave ports.
pvbus_s_ace_lite_plus_dvm_0 PVBus Slave Memory bus interface that implements ACE lite and DVM protocol.
pvbus_s_ace_lite_plus_dvm_1 PVBus Slave Memory bus interface that implements ACE lite and DVM protocol.
pvbus_s_ace_lite_plus_dvm_2 PVBus Slave Memory bus interface that implements ACE lite and DVM protocol.
reset_in Signal Slave Signal to reset the CCI.
reset_state_of_ace_lite_ports[3] Signal Slave This port can be connected to the reset signals of the system attached to ACE-Lite ports 0,1,2

Table 3-287 Parameters for CCI400

Name Type Default value Description
acchannelen int 0x1f For each upstream port, determine if it is enabled or not w.r.t. snoop requests.
barrierterminate int 0x7 For each downstream port, determine if barriers will be terminated at that port.
broadcastcachemain int 0x0 For each downstream port a bit determines if broadcast cache maintenance operations are forwarded down that port.
bufferableoverride int 0x0 For each downstream port, determine if all transactions will be forced to non-bufferable.
cache_state_modelled bool 0x1 Model the cache state.
force_on_from_start bool 0x0 The CCI will normally start up with snooping disabled, however, using this then we allow the model to start up as enabled without having to program it. This is only setup at simulation reset and not at signal reset. If the upstreams can ever be held in reset then you *must* connect the reset_state_of_ace_lite_ports[], lint_ace_3_reset_state and lint_ace_4_reset_state so that it knows when to disable snoops to the upstream systems. Otherwise, the upstream system will receive snoop messages whilst in reset and it will complain that it 'received a snoop request whilst it was in reset'.
log_enabled int 0x1 Enable log messages from the CCI register file. Log level 0 means do not print anything, 1 means print only access violations, 2 means also print writes, 3 means print reads as well.
periphbase int 0x2c000000 Value for PERIPHBASE. Only bits [39:16] are used. This value may be overriden by an input on the periphbase port
revision string "r0p0" Revision of the CCI400
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