3.4.39 ARMCortexR52x1CT

ARMCortexR52x1CT CPU component. This model is written in C++.

Note:

  • The following components also exist:

    • ARMCortexR52x2CT.
    • ARMCortexR52x3CT.
    • ARMCortexR52x4CT.
  • The per-core parameters are preceded by cpun., where n identifies the core (0-3).

ARMCortexR52x1CT - about

The model has the following limitations:

  • It does not implement redundant cores for Dual-Core Lock-Step operations.
  • It does not implement the Low Power Interface to wake up the target core on receiving a wake_request signal from the GIC distributor.
  • TCMs are modeled internally and the model does not support external TCMs or the ports associated with them.
  • It does not support running Software Test Libraries (STLs).

Additional parameter information

semihosting-cmd_line
The value of argv[0] points to the first command-line argument, not to the name of an image.
vfp-enable_at_reset
This is a model-specific behavior with no hardware equivalent.

Table 3-175 Ports

Name Protocol Type Description
cfgdbgromaddr Value_64 Slave Debug ROM base address.
cfgdbgromaddrv Signal Slave Debug ROM base address valid.
cfgendianess[1] Signal Slave This signal if for EE bit initialisation.
cfgperiphbase Value_64 Slave This port sets the base address of private peripheral region.
cfgthumbexceptions[1] Signal Slave This signal provides default exception handling state.
cfgvectable[1] Value_64 Slave Reset vector base address.
clk_in ClockSignal Slave The clock signal connected to the clk_in port is used to determine the rate at which the core executes instructions.
clrexmonack Signal Master Acknowledge handshake signal for the clrexmonreq signal
clrexmonreq Signal Slave Signals the clearing of an external global exclusive monitor
cntvalueb CounterInterface Slave Interface to SoC level counter module.
commrx[1] Signal Master Receive portion of Data Transfer Register full.
commtx[1] Signal Master Transmit portion of Data Transfer Register empty.
cpuhalt[1] Signal Slave Raising this signal will put the core into halt mode.
cpuporeset[1] Signal Slave Power on reset. Initializes all the processor logic, including debug logic.
cti[1] v8EmbeddedCrossTrigger_controlprotocol Master Cross trigger matrix port.
dbgack[1] Signal Master External debug interface.
dbgen[1] Signal Slave External debug interface.
dbgnopwrdwn[1] Signal Master There is no support for PChannel in CortexR52. These signals relate to core power down. Equivalent to COREPACTIVEx
dbgpwrupreq[1] Signal Master Debug power up request.
dev_debug_s PVBus Slave External debug interface.
edbgrq[1] Signal Slave External debug interface.
event Signal Peer This peer port of event input (and output) is for wakeup from WFE.
ext_slave_s PVBus Slave External Slave port. Equivalent to AXIS port
extppi_in_0[9] Signal Slave Core 0 external ppi signals.
flash_m[1] PVBus Master Flash Port.
gdu_external_m GICv3Comms Master GDU external messaging port.
hiden[1] Signal Slave External debug interface.
hniden[1] Signal Slave External debug interface.
llpp_m[1] PVBus Master LLPP (Low-Latency Peripheral Port).
memorymapped_debug_s PVBus Slave External debug interface.
niden[1] Signal Slave External debug interface.
presetdbg Signal Slave Initialize the shared debug APB, Cross Trigger Interface (CTI), and Cross Trigger Matrix (CTM) logic.
pvbus_core_m[1] PVBus Master The core will generate bus requests on this port. Equivalent to AXIM port
reset[1] Signal Slave Raising this signal will put the core into reset mode.
sei[1] Signal Slave Per core virtual System Error physical pins.
spi_in[960] Signal Slave Shared peripheral interrupts.
standbywfe[1] Signal Master This signal indicates if a core is in WFE state.
standbywfi[1] Signal Master This signal indicates if a core is in WFI state.
ticks[1] InstructionCount Master This port should be connected to one of the two ticks ports on a 'visualisation' component, in order to display a running instruction count.
topreset Signal Slave This signal resets timer and interrupt controller.
vsei[1] Signal Slave Per core virtual System Error physical pins.
warmrstreq[1] Signal Master Warm reset request from core.

Table 3-176 Parameters for ARM_CortexR52

Name Type Default value Description
CLUSTER_ID int 0x0 CLUSTER_ID[15:8] equivalent to CFGMPIDRAFF2, CLUSTER_ID[7:0] equivalent to CFGMPIDRAFF1
DBGROMADDR int 0x0 Equivalent to CFGDBGROMADDR
DBGROMADDRV bool 0x0 If true, set bits[1:0] of the CP15 DBGDRAR to indicate that the address is valid
PERIPHBASE int 0x13080000 Equivalent to CFGPERIPHBASE
cluster_utid int 0x0 Equivalent to CFGCLUSTERUTID
cpi_div int 0x1 Divider for calculating CPI (Cycles Per Instruction)
cpi_mul int 0x1 Multiplier for calculating CPI (Cycles Per Instruction)
dcache-prefetch_enabled bool 0x0 Enable simulation of data cache prefetching. This is only used when dcache-state_modelled=true
dcache-read_access_latency int 0x0 L1 D-Cache timing annotation latency for read accesses given in ticks per access (of size dcache-read_bus_width_in_bytes). If this parameter is non-zero, per-access latencies will be used instead of per-byte even if dcache-read_latency is set. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus, this is only used when dcache-state_modelled=true.
dcache-state_modelled bool 0x0 Set whether D-cache has stateful implementation
dcache-write_access_latency int 0x0 L1 D-Cache timing annotation latency for write accesses given in ticks per access (of size dcache-write_bus_width_in_bytes). If this parameter is non-zero, per-access latencies will be used instead of per-byte even if dcache-write_latency is set. This is only used when dcache-state_modelled=true.
enable_simulation_performance_optimizations bool 0x1 With this option enabled, the model will run more quickly, but be less accurate to exact CPU behavior. The model will still be functionally accurate for software, but may increase differences seen between hardware behavior and model behavior for certain workloads (it changes the micro-architectural value of stage12_tlb_size parameter to 1024).
flash_protection_enable_at_reset bool 0x0 Equivalent to CFGFLASHPROTEN
has_export_m_port bool 0x1 The interrupt distributor has an optional interrupt export port for routing interrupts to an external device
has_flash_protection bool 0x1 Equivalent to CFGFLASHPROTIMP
icache-prefetch_enabled bool 0x0 Enable simulation of instruction cache prefetching. This is only used when icache-state_modelled=true.
icache-read_access_latency int 0x0 L1 I-Cache timing annotation latency for read accesses given in ticks per access (of size icache-read_bus_width_in_bytes). If this parameter is non-zero, per-access latencies will be used instead of per-byte even if icache-read_latency is set. This is in addition to the hit or miss latency, and intended to correspond to the time taken to transfer across the cache upstream bus, this is only used when icache-state_modelled=true.
icache-state_modelled bool 0x0 Set whether I-cache has stateful implementation
memory.ext_slave_base int 0x0 Equivalent to CFGAXISTCMBASEADDR
memory.flash_base int 0x0 Equivalent to CFGFLASHBASEADDR
memory.flash_size int 0x4000000 Equivalent to CFGFLASHIMP. memory.flash_size = 0 => CFGFLASHIMP = false
num_protection_regions_s1 int 0x10 Number of v8-R protection regions
num_protection_regions_s2 int 0x10 Number of v8-R hyp protection regions
num_spi int 0x3c0 Number of interrupts (SPI) into the internal GIC controller
ram_protection_enable_at_reset bool 0x0 Equivalent to CFGRAMPROTEN

Table 3-177 Parameters for gic_iri

Name Type Default value Description
gic_iri.A3-affinity-supported bool 0x0 Device supports affinity level 3 values that are non-zero.
gic_iri.ARE-fixed-to-one bool 0x0 GICv2 compatibility is not supported and GICD_CTLR.ARE_* is always one
gic_iri.CPU-affinities string "" A comma separated list of dotted quads containing the affinities of all PEs connected to this IRI. If CPU-affinities-file is specified, this parameter is ignored.
gic_iri.CPU-affinities-file string "" A file containing comma separated list of dotted quads containing the affinities of all PEs connected to this IRI. If this parameter is specified, CPU-affinities parameter will be ignored even when it is given.
gic_iri.DPG-ARE-only bool 0x0 Limit application of DPG bits to interrupt groups for which ARE=1
gic_iri.DPG-bits-implemented bool 0x0 Enable implementation of interrupt group participation bits or DPG bits in GICR_CTLR
gic_iri.DS-fixed-to-zero bool 0x0 Enable/disable support of single security state
gic_iri.GICD-alias int 0x0 In GICv2 mode: the base address for a 4k page alias of the first 4k of the Distributor page, in GICv3 mode. the base address of a 64KB page containing message based SPI signalling register aliases(0:Disabled)
gic_iri.GICD-legacy-registers-as-reserved bool 0x0 When ARE is RAO/WI, makes superfluous registers in GICD reserved ( including for the purpose of STATUSR updates)
gic_iri.GICD_ITARGETSR-RAZWI bool 0x0 If true, the GICD_ITARGETS registers are RAZ/WI
gic_iri.GICD_PIDR int 0x0 The value for the GICD_PIDR registers, if non-zero. Note: fixed fields (device type etc.) will be overriden in this value.
gic_iri.GICR_PIDR int 0x0 The value for the GICR_PIDR registers, if non-zero. Note: fixed fields (device type etc.) will be overriden in this value.
gic_iri.GICR_PROPBASER-read-only bool 0x0 GICR_PROPBASER register is read-only.
gic_iri.GICR_PROPBASER-reset-value int 0x0 Value of GICR_PROPBASER on reset.
gic_iri.GITS_BASER0-entry-bytes int 0x8 Number of bytes required per entry for GITS_BASER0 register.
gic_iri.GITS_BASER0-indirect-RAZ bool 0x0 Indirect field for GITS_BASER0 register is RAZ/WI.
gic_iri.GITS_BASER0-type int 0x0 Type field for GITS_BASER0 register. 0 = Unimplemented; 1 = Devices; 2 = Virtual Processors; 3 = Physical Processors; 4 = Collections
gic_iri.GITS_BASER1-entry-bytes int 0x8 Number of bytes required per entry for GITS_BASER1 register.
gic_iri.GITS_BASER1-indirect-RAZ bool 0x0 Indirect field for GITS_BASER1 register is RAZ/WI.
gic_iri.GITS_BASER1-type int 0x0 Type field for GITS_BASER1 register. 0 = Unimplemented; 1 = Devices; 2 = Virtual Processors; 3 = Physical Processors; 4 = Collections
gic_iri.GITS_BASER2-entry-bytes int 0x8 Number of bytes required per entry for GITS_BASER2 register.
gic_iri.GITS_BASER2-indirect-RAZ bool 0x0 Indirect field for GITS_BASER2 register is RAZ/WI.
gic_iri.GITS_BASER2-type int 0x0 Type field for GITS_BASER2 register. 0 = Unimplemented; 1 = Devices; 2 = Virtual Processors; 3 = Physical Processors; 4 = Collections
gic_iri.GITS_BASER3-entry-bytes int 0x8 Number of bytes required per entry for GITS_BASER3 register.
gic_iri.GITS_BASER3-indirect-RAZ bool 0x0 Indirect field for GITS_BASER3 register is RAZ/WI.
gic_iri.GITS_BASER3-type int 0x0 Type field for GITS_BASER3 register. 0 = Unimplemented; 1 = Devices; 2 = Virtual Processors; 3 = Physical Processors; 4 = Collections
gic_iri.GITS_BASER4-entry-bytes int 0x8 Number of bytes required per entry for GITS_BASER4 register.
gic_iri.GITS_BASER4-indirect-RAZ bool 0x0 Indirect field for GITS_BASER4 register is RAZ/WI.
gic_iri.GITS_BASER4-type int 0x0 Type field for GITS_BASER4 register. 0 = Unimplemented; 1 = Devices; 2 = Virtual Processors; 3 = Physical Processors; 4 = Collections
gic_iri.GITS_BASER5-entry-bytes int 0x8 Number of bytes required per entry for GITS_BASER5 register.
gic_iri.GITS_BASER5-indirect-RAZ bool 0x0 Indirect field for GITS_BASER5 register is RAZ/WI.
gic_iri.GITS_BASER5-type int 0x0 Type field for GITS_BASER5 register. 0 = Unimplemented; 1 = Devices; 2 = Virtual Processors; 3 = Physical Processors; 4 = Collections
gic_iri.GITS_BASER6-entry-bytes int 0x8 Number of bytes required per entry for GITS_BASER6 register.
gic_iri.GITS_BASER6-indirect-RAZ bool 0x0 Indirect field for GITS_BASER6 register is RAZ/WI.
gic_iri.GITS_BASER6-type int 0x0 Type field for GITS_BASER6 register. 0 = Unimplemented; 1 = Devices; 2 = Virtual Processors; 3 = Physical Processors; 4 = Collections
gic_iri.GITS_BASER7-entry-bytes int 0x8 Number of bytes required per entry for GITS_BASER7 register.
gic_iri.GITS_BASER7-indirect-RAZ bool 0x0 Indirect field for GITS_BASER7 register is RAZ/WI.
gic_iri.GITS_BASER7-type int 0x0 Type field for GITS_BASER7 register. 0 = Unimplemented; 1 = Devices; 2 = Virtual Processors; 3 = Physical Processors; 4 = Collections
gic_iri.GITS_PIDR int 0x0 The value for the GITS_PIDR registers, if non-zero. Note: fixed fields (device type etc.) will be overriden in this value.
gic_iri.ICFGR-PPI-mask int 0xaaaaaaaa Mask for writes to ICFGR registers that configure PPIs
gic_iri.ICFGR-PPI-reset int 0x0 Reset value for ICFGR regesters that configure PPIs
gic_iri.ICFGR-SGI-mask int 0x0 Mask for writes to ICFGR registers that configure SGIs
gic_iri.ICFGR-SGI-reset int 0xaaaaaaaa Reset value for ICFGR registers that configure SGIs
gic_iri.ICFGR-SPI-mask int 0xaaaaaaaa Mask for writes to ICFGR registers that configure SPIs
gic_iri.ICFGR-SPI-reset int 0x0 Reset value for ICFGR regesters that configure SPIs
gic_iri.ICFGR-rsvd-bit bool 0x0 If ARE=0, the value of reserved bits i.e. bit 0,2,4..30 of ICFGRn for n>0
gic_iri.IGROUP-PPI-mask int 0xffff Mask for writes to PPI bits in IGROUP registers
gic_iri.IGROUP-PPI-reset int 0x0 Reset value for SGI bits in IGROUP registers
gic_iri.IGROUP-SGI-mask int 0xffff Mask for writes to SGI bits in IGROUP registers
gic_iri.IGROUP-SGI-reset int 0x0 Reset value for SGI bits in IGROUP registers
gic_iri.IIDR int 0x0 GICD_IIDR and GICR_IIDR value
gic_iri.IRI-ID-bits int 0x10 Number of bits used to represent interrupts IDs in the Distributor and Redistributors, forced to 10 if LPIs are not supported
gic_iri.IROUTER-IRM-RAZ-WI bool 0x0 GICD_IROUTERn.InterruptRoutingMode is RAZ/WI
gic_iri.ITS-BASER-force-page-alignement bool 0x1 Force alignement of address writen to a GITS_BASER register to the page size configured
gic_iri.ITS-ID-bits int 0x10 Number of interrupt bits supported by ITS.
gic_iri.ITS-MOVALL-update-collections bool 0x0 Whether MOVALL command updates the collection entires
gic_iri.ITS-TRANSLATE64R bool 0x0 Add an implementation specific register at 0x10008 supporting 64 bit TRANSLATER (dev[63:32], interupt[31:0])
gic_iri.ITS-collection-ID-bits int 0x0 Number of collection bits supported by ITS (optional parameter, 0 => 16bits support and GITS_TYPER.CIL=0
gic_iri.ITS-count int 0x0 Number of Interrupt Translation Services to be instantiated (0=none)
gic_iri.ITS-cumulative-collection-tables bool 0x1 When true, the supported amount of collections is the sum of GITS_TYPER.HCC and the number of collections supported in memory, otherwise, simply the number supported in memory only. Irrelevant when HCC=0
gic_iri.ITS-device-bits int 0x10 Number of bits supported for ITS device IDs.
gic_iri.ITS-entry-size int 0x8 Number of bytes required to store each entry in the ITT tables.
gic_iri.ITS-hardware-collection-count int 0x0 Number of hardware collections held exclusively in the ITS
gic_iri.ITS-legacy-iidr-typer-offset bool 0x0 Put the GITS_IIDR and GITS_TYPER registers at their older offset of 0x8 and 0x4 respectively
gic_iri.ITS-shared-vPE-table int 0x0 Number of affinity levels to which the vPE configuration table is shared. This parameter is valid when has-gicv4.1 is true.
gic_iri.ITS-threaded-command-queue bool 0x1 Enable execution of ITS commands in a separate thread which is sometimes required for cosimulation
gic_iri.ITS-use-physical-target-addresses bool 0x1 Use physical hardware adresses for targets in ITS commands -- must be true for distributed implementations
gic_iri.ITS-vmovp-bit bool 0x0 Device supports software issuing a VMOVP to only one of the ITSs that has a mapping for a vPE. The device itself ensures synchronization of the VMOVP command across all ITSs that have mapping for that vPE.
gic_iri.ITS0-base int 0x0 Register base address for ITS0 (automatic if 0).
gic_iri.ITS1-base int 0x0 Register base address for ITS1 (automatic if 0).
gic_iri.ITS2-base int 0x0 Register base address for ITS2 (automatic if 0).
gic_iri.ITS3-base int 0x0 Register base address for ITS3 (automatic if 0).
gic_iri.LPI-cache-check-data bool 0x0 Enable Cached LPI data against memory checking when available for cache type
gic_iri.LPI-cache-type int 0x1 Cache type for LPIs, 0:No caching, 1:Full caching
gic_iri.MSI_IIDR int 0x0 Value returned in MSI_IIDR registers.
gic_iri.MSI_NS-frame0-base int 0x0 If non-zero, sets the base address used for non-secure MSI frame 0 registers.
gic_iri.MSI_NS-frame0-max-SPI int 0x0 Maximum SPI ID supported by non-secure MSI frame 0. Set to 0 to disable frame.
gic_iri.MSI_NS-frame0-min-SPI int 0x0 Minimum SPI ID supported by non-secure MSI frame 0. Set to 0 to disable frame.
gic_iri.MSI_NS-frame1-base int 0x0 If non-zero, sets the base address used for non-secure MSI frame 1 registers.
gic_iri.MSI_NS-frame1-max-SPI int 0x0 Maximum SPI ID supported by non-secure MSI frame 1. Set to 0 to disable frame.
gic_iri.MSI_NS-frame1-min-SPI int 0x0 Minimum SPI ID supported by non-secure MSI frame 1. Set to 0 to disable frame.
gic_iri.MSI_NS-frame2-base int 0x0 If non-zero, sets the base address used for non-secure MSI frame 2 registers.
gic_iri.MSI_NS-frame2-max-SPI int 0x0 Maximum SPI ID supported by non-secure MSI frame 2. Set to 0 to disable frame.
gic_iri.MSI_NS-frame2-min-SPI int 0x0 Minimum SPI ID supported by non-secure MSI frame 2. Set to 0 to disable frame.
gic_iri.MSI_NS-frame3-base int 0x0 If non-zero, sets the base address used for non-secure MSI frame 3 registers.
gic_iri.MSI_NS-frame3-max-SPI int 0x0 Maximum SPI ID supported by non-secure MSI frame 3. Set to 0 to disable frame.
gic_iri.MSI_NS-frame3-min-SPI int 0x0 Minimum SPI ID supported by non-secure MSI frame 3. Set to 0 to disable frame.
gic_iri.MSI_NS-frame4-base int 0x0 If non-zero, sets the base address used for non-secure MSI frame 4 registers.
gic_iri.MSI_NS-frame4-max-SPI int 0x0 Maximum SPI ID supported by non-secure MSI frame 4. Set to 0 to disable frame.
gic_iri.MSI_NS-frame4-min-SPI int 0x0 Minimum SPI ID supported by non-secure MSI frame 4. Set to 0 to disable frame.
gic_iri.MSI_NS-frame5-base int 0x0 If non-zero, sets the base address used for non-secure MSI frame 5 registers.
gic_iri.MSI_NS-frame5-max-SPI int 0x0 Maximum SPI ID supported by non-secure MSI frame 5. Set to 0 to disable frame.
gic_iri.MSI_NS-frame5-min-SPI int 0x0 Minimum SPI ID supported by non-secure MSI frame 5. Set to 0 to disable frame.
gic_iri.MSI_NS-frame6-base int 0x0 If non-zero, sets the base address used for non-secure MSI frame 6 registers.
gic_iri.MSI_NS-frame6-max-SPI int 0x0 Maximum SPI ID supported by non-secure MSI frame 6. Set to 0 to disable frame.
gic_iri.MSI_NS-frame6-min-SPI int 0x0 Minimum SPI ID supported by non-secure MSI frame 6. Set to 0 to disable frame.
gic_iri.MSI_NS-frame7-base int 0x0 If non-zero, sets the base address used for non-secure MSI frame 7 registers.
gic_iri.MSI_NS-frame7-max-SPI int 0x0 Maximum SPI ID supported by non-secure MSI frame 7. Set to 0 to disable frame.
gic_iri.MSI_NS-frame7-min-SPI int 0x0 Minimum SPI ID supported by non-secure MSI frame 7. Set to 0 to disable frame.
gic_iri.MSI_PIDR int 0x0 The value for the MSI_PIDR registers, if non-zero and distributor supports GICv2m. Note: fixed fields (device type etc.) will be overriden in this value.
gic_iri.MSI_S-frame0-base int 0x0 If non-zero, sets the base address used for secure MSI frame 0 registers.
gic_iri.MSI_S-frame0-max-SPI int 0x0 Maximum SPI ID supported by secure MSI frame 0. Set to 0 to disable frame.
gic_iri.MSI_S-frame0-min-SPI int 0x0 Minimum SPI ID supported by secure MSI frame 0. Set to 0 to disable frame.
gic_iri.MSI_S-frame1-base int 0x0 If non-zero, sets the base address used for secure MSI frame 1 registers.
gic_iri.MSI_S-frame1-max-SPI int 0x0 Maximum SPI ID supported by secure MSI frame 1. Set to 0 to disable frame.
gic_iri.MSI_S-frame1-min-SPI int 0x0 Minimum SPI ID supported by secure MSI frame 1. Set to 0 to disable frame.
gic_iri.MSI_S-frame2-base int 0x0 If non-zero, sets the base address used for secure MSI frame 2 registers.
gic_iri.MSI_S-frame2-max-SPI int 0x0 Maximum SPI ID supported by secure MSI frame 2. Set to 0 to disable frame.
gic_iri.MSI_S-frame2-min-SPI int 0x0 Minimum SPI ID supported by secure MSI frame 2. Set to 0 to disable frame.
gic_iri.MSI_S-frame3-base int 0x0 If non-zero, sets the base address used for secure MSI frame 3 registers.
gic_iri.MSI_S-frame3-max-SPI int 0x0 Maximum SPI ID supported by secure MSI frame 3. Set to 0 to disable frame.
gic_iri.MSI_S-frame3-min-SPI int 0x0 Minimum SPI ID supported by secure MSI frame 3. Set to 0 to disable frame.
gic_iri.MSI_S-frame4-base int 0x0 If non-zero, sets the base address used for secure MSI frame 4 registers.
gic_iri.MSI_S-frame4-max-SPI int 0x0 Maximum SPI ID supported by secure MSI frame 4. Set to 0 to disable frame.
gic_iri.MSI_S-frame4-min-SPI int 0x0 Minimum SPI ID supported by secure MSI frame 4. Set to 0 to disable frame.
gic_iri.MSI_S-frame5-base int 0x0 If non-zero, sets the base address used for secure MSI frame 5 registers.
gic_iri.MSI_S-frame5-max-SPI int 0x0 Maximum SPI ID supported by secure MSI frame 5. Set to 0 to disable frame.
gic_iri.MSI_S-frame5-min-SPI int 0x0 Minimum SPI ID supported by secure MSI frame 5. Set to 0 to disable frame.
gic_iri.MSI_S-frame6-base int 0x0 If non-zero, sets the base address used for secure MSI frame 6 registers.
gic_iri.MSI_S-frame6-max-SPI int 0x0 Maximum SPI ID supported by secure MSI frame 6. Set to 0 to disable frame.
gic_iri.MSI_S-frame6-min-SPI int 0x0 Minimum SPI ID supported by secure MSI frame 6. Set to 0 to disable frame.
gic_iri.MSI_S-frame7-base int 0x0 If non-zero, sets the base address used for secure MSI frame 7 registers.
gic_iri.MSI_S-frame7-max-SPI int 0x0 Maximum SPI ID supported by secure MSI frame 7. Set to 0 to disable frame.
gic_iri.MSI_S-frame7-min-SPI int 0x0 Minimum SPI ID supported by secure MSI frame 7. Set to 0 to disable frame.
gic_iri.PA_SIZE int 0x30 Number of valid bits in physical address
gic_iri.PPI-implemented-mask int 0xffff Mask of PPIs that are implemented. One bit per PPI bit 0 == PPI 16 (first PPI). This will affect other masks.
gic_iri.SPI-count int 0xe0 Number of SPIs that are implemented.
gic_iri.SPI-message-based-support bool 0x1 Distributor supports meassage based signaling of SPI
gic_iri.SPI-unimplemented string "" A comma spearated list of unimplemented SPIs ranges for sparse SPI defintion(for ex: '35, 39-42, 73)'
gic_iri.STATUSR-implemented bool 0x1 Determines whether the GICR_STATUSR register is implemented.
gic_iri.allow-LPIEN-clear bool 0x0 Allow RW behaviour on GICR_CTLR.LPIEN isntead of set once
gic_iri.chip-id int 0x0 Chip ID when multichip operation is enabled.
gic_iri.common-lpi-configuration int 0x0 Describes which re-distributors share (and must be configured with the same) LPI configuration table as described in GICR_TYPER( 0:All, 1:A.x.x.x, 2:A.B.x.x, 3:A.B.C.x
gic_iri.common-vPE-table-affinity string "" Affinity value in the form of 'a.b.c.d' under which vPE configuration table is shared among redistributors where level to be shared is defined by ITS-shared-vPE-table. This parameter is valid when has-gicv4.1 is true.
gic_iri.consolidators string "" Specify consolidators' base addresses, interrupt line counts and base interrupt IDs, in the form 'baseAddr0:itlineCount0:baseINTID0, baseAddr1:itlineCount1:baseINTID1, [etc]' (eg '0x3f100000:64:4096, 0x3f200000:64:4224'). The consolidators' count is inferred from the list (maximum of 4). If not specified, the component contains no consolidators.
gic_iri.delay-ITS-accesses bool 0x1 Delay accesses from the ITS until GICR_SYNCR is read.
gic_iri.delay-redistributor-accesses bool 0x1 Delay memory accesses from the redistributor until GICR_SYNCR is read.
gic_iri.direct-lpi-support bool 0x0 Enable support for LPI operations through GICR registers
gic_iri.enable-multichip-operation bool 0x0 Enables multi-chip operation between Distributors in distributed GIC IRI
gic_iri.enable_protocol_checking bool 0x0 Enable/disable protocol checking at cpu interface
gic_iri.enabled bool 0x1 Enable GICv3 functionality; when false the component is inactive.
gic_iri.extended-ppi-count int 0x0 Number of extended PPI supported
gic_iri.extended-spi-count int 0x0 Number of extended SPI supported
gic_iri.fixed-routed-spis string "" Value of IROUTER[n] register in the form 'n=a.b.c.d, n=*'. The RM bit of IROUTER is 0 when n=a.b.c.d is used else 1 when n=* is used. n can be >= 32 and <= 1019
gic_iri.gicv2-only bool 0x0 If true, when using the GICv3 model, pretend to be a GICv2 system
gic_iri.has-two-security-states bool 0x1 If true, has two security states
gic_iri.has_VPENDBASER-dirty-flag-on-load bool 0x0 GICR_VPENDBASER.Dirty reflects transient loading state when valid=1
gic_iri.has_mpam bool 0x0 Enable MPAM support on ITS and RDs
gic_iri.ignore-generate-sgi-when-no-are bool 0x0 Ignore GenerateSGI packets coming form the CPU interface if both ARE_S and ARE_NS are 0
gic_iri.irouter-default-mask string "" Default Mask value for IROUTER[32..1019] register in the form 'a.b.c.d'
gic_iri.irouter-default-reset string "" Default Reset Value of IROUTER[32..1019] register in the form 'a.b.c.d' or *
gic_iri.irouter-mask-values string "" Mask Value of IROUTER[n] register in the form 'n=a.b.c.d'.n can be >= 32 and <= 1019
gic_iri.irouter-reset-values string "" Reset Value of IROUTER[n] register in the form 'n=a.b.c.d or n=*'.n can be >= 32 and <= 1019
gic_iri.legacy-sgi-enable-rao bool 0x0 Enables for SGI associated with an ARE=0 regime are RAO/WI
gic_iri.local-SEIs bool 0x0 Generate SEI to signal internal issues
gic_iri.local-VSEIs bool 0x0 Generate VSEI to signal internal issues
gic_iri.lockable-SPI-count int 0x0 Number of SPIs that are locked down when CFGSDISABLE signal is asserted. Only applies for GICv2.
gic_iri.monolithic bool 0x0 Indicate that the implementation is not distributed
gic_iri.mpam_max_partid int 0xffff Maximum valid PARTID
gic_iri.mpam_max_pmg int 0xff Maximum valid PMG
gic_iri.non-ARE-core-count int 0x8 Maximum number of non-ARE cores; normally used to pass the cluster-level NUM_CORES parameter to the top-level redistributor.
gic_iri.outer-cacheability-support bool 0x0 Allow configuration of outer cachability attributes in ITS and Redistributor
gic_iri.output_attributes string "ExtendedID[62:55]=MPAM_PMG, ExtendedID[54:39]=MPAM_PARTID, ExtendedID[38]=MPAM_NS" User-defined transform to be applied to bus attributes like MasterID, ExtendedID or UserFlags. Currently, only works for MPAM Attributes encoding into bus attributes.
gic_iri.print-memory-map bool 0x0 Print memory map to stdout
gic_iri.priority-bits int 0x5 Number of implemented priority bits
gic_iri.processor-numbers string "" Specify processor numbers (as appears in GICR_TYPER) in the form 0.0.0.0=0,0.0.0.1=1 etc.) If not specified, will number processors starting at 0.
gic_iri.redistributor-threaded-sync bool 0x1 Enable execution of redistributor delayed transactions in a separate thread which is sometimes required for cosimulation
gic_iri.reg-base int 0x2c010000 Base for decoding GICv3 registers.
gic_iri.reg-base-per-redistributor string "" Base address for each redistributor in the form '0.0.0.0=0x2c010000, 0.0.0.1=0x2c020000'. All redistributors must be specified and this overrides the reg-base parameter (except that reg-base will still be used for the top-level redistributor).
gic_iri.sgi-range-selector-support bool 0x0 Device has support for the Range Selector feature for SGI
gic_iri.single-set-support bool 0x0 When true, forces redistributors to recall interrupts with a clear rather than issue a second Set command
gic_iri.supports-shareability bool 0x1 Device supports shareability attributes on outgoing memory bus (i.e. is modelling an ACElite port rather than an AXI4 port).
gic_iri.trace-speculative-lpi-property-update bool 0x0 Trace LPI propery updates performed on speculative accesses (useful for debuging LPI)
gic_iri.virtual-lpi-support bool 0x0 GICv4 Virtual LPIs and Direct injection of Virtual LPIs supported
gic_iri.virtual-priority-bits int 0x5 Number of implemented virtual priority bits
gic_iri.wakeup-on-reset bool 0x0 Go against specification and start redistributors in woken-up state at reset. This allows software that was written for previous versions of the GICv3 specification to work correctly. This should not be used for production code or when the distributor is used separately from the core fast model.
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