3.10.6 CCI550

Cache Coherent Interconnect for AXI4 ACE. This model is written in C++.

CCI550 contains the following CADI targets:

  • CCI550

CCI550 contains the following MTI components:

Model limitations

Address Decoder
  • Only supports striping down to 4KiB.
  • If the address decoder aborts the access, returns SLVERR rather than DECERR.
Interfaces
The model does not implement the Q-Channel and P-Channel interfaces.
Performance Monitoring Unit
  • PMU counters recognize only a few event sources:
    • Slave interface events:
      3ReadOnce.
      4ReadClean, ReadShared, ReadNotSharedDirty, ReadUnique.
      5MakeUnique, CleanUnique.
      6CleanInvalid, CleanShared, MakeInvalid.
      7DVM transaction received from upstream.
      9Read data that is satisfied by a snoop request.
    • No events are implemented for the global events or for the master events.
  • The PMU does not implement the event bus (EVNTBUS).
Reset signal sampling
The configuration ports acchannelensx[] are sampled in the hardware when coming out of reset. In the model, these ports are sampled at the first transaction to a pvbus_s port or to the register file.
Status Register, change-pending, and DVM messages
The Status Register provides information on when the last transaction that could have observed an old value of a snoop or DVM enable has finished in the upstream system. Therefore a port that has been disabled can now have the system upstream of that port turned off. The model does not track DVM messages in the upstream system.
Snoop filter RAMs
  • The CCI-550 hardware has a snoop filter that reduces the number of snoop requests that the interconnect has to make. The model does not have a snoop filter and could make more snoop requests than the hardware would. This difference has no programmer-visible effect.
  • The Status Register fields that relate to the power state of the Snoop filter RAMs are undefined.
Registers
The following registers provide storage but have no effect on the model.
  • QoS registers.
  • Interface monitor registers. These registers are intended for silicon debug.

Table 3-290 Ports

Name Protocol Type Description
acchannelensx[7] Value Slave The acchannelensx[N] pins are used to tell the interconnect if the upstream system will accept snoops and/or DVM messages.
address_decoder CCI500_AddressDecoderProtocol Master An address decoder can be attached to the address_decoder port to choose which pvbus_s port a downstream transaction will go out of. If you do not connect an address decoder then all transactions will go out of port 0.
dbgen Signal Slave Invasive debug enable.
errirq Signal Master Some async error was detected.
evntcntoverflow[8] Signal Master The output interrupts of the event counters.
niden Signal Slave Non-invasive debug enable.
pvbus_m[7] PVBus Master The downstream master ports.
pvbus_register_file_s PVBus Slave The slave port of the register file.
pvbus_s[7] PVBus Slave Bus slave ports.
reset_in Signal Slave Reset the interconnect.
reset_state_of_upstream_port[7] Signal Slave Tell the interconnect the reset state of the upstream ports, this can be used by the interconnect to check some aspects of the reset sequencing. If you are using force_on_from_start then you _must_ connect these pins.
sci_s[7] SystemCoherencyInterface Slave The System Coherency Interface bus. For those upstream ports that have a corresponding bit set in the bitmap of si_system_coherency_interface then the corresponding sci_m port can be used to move the upstream system into and out of the coherency domain.
spiden Signal Slave Secure privileged invasive debug enable.
spniden Signal Slave Secure privileged non-invasive debug enable.

Table 3-291 Parameters for CCI550

Name Type Default value Description
acchannelens0 int 0x0 For upstream port 0 determine if it is enabled or not w.r.t. snoop requests.
acchannelens1 int 0x0 For upstream port 1 determine if it is enabled or not w.r.t. snoop requests.
acchannelens2 int 0x0 For upstream port 2 determine if it is enabled or not w.r.t. snoop requests.
acchannelens3 int 0x0 For upstream port 3 determine if it is enabled or not w.r.t. snoop requests.
acchannelens4 int 0x0 For upstream port 4 determine if it is enabled or not w.r.t. snoop requests.
acchannelens5 int 0x0 For upstream port 5 determine if it is enabled or not w.r.t. snoop requests.
acchannelens6 int 0x0 For upstream port 6 determine if it is enabled or not w.r.t. snoop requests.
addr_width int 0x28 The bit-width of the address that the CCI can accept.
cache_state_modelled bool 0x1 Model the cache state.
dbgen bool 0x1 Invasive debug enable. If true, enables the counting of PMU events.
enable_logger bool 0x0 Enable PVBusLoggers for the downstream ports in the CCI model.
force_on_from_start bool 0x0 The interconnect will normally start up with snooping/DVM disabled. The parameter si_system_coherency_interface determines which connections are managed by the System Coherency Interface (SCI). For connections that are managed by SCI, then this parameter has no effect. For all other connections, this parameter enables the upstream system of a port to be snooped if the upstream is not in reset and if ACCHANNELENSx allows it. No software driver for the interconnect is needed. Any non-SCI port that could go into reset must have 'reset_state_of_upstream_port[]' reflect the reset state of that upstream system. Otherwise, the upstream system may receive snoop/DVM messages whilst in reset and may complain that it 'received a snoop request whilst it was in reset'. Do not use if software is directly controlling the interconnect. This option does not disavow the responsibility of the upstream system to clean any shared dirty data from its caches before going into reset.
niden bool 0x1 Whether non-secure events are allowed to be counted in the performance monitor
num_ace_lite_ports int 0x5 The bottom num_ace_lite_ports are ACE-Lite+DVM.
num_ace_ports int 0x2 The top num_ace_ports are ACE and support full coherency.
number_of_phantom_entries int 0x20 Number of phantom entries in the cache. Phantom entries are used by certain cache operations to hold temporary data. Usually this should be left at the default value which is safe for all systems containing up to 32 masters.
qos_threshold_upper int 0xc Reset value for the QoS threshold register.
reentrancy_support string "env" Must be one of: on/off/cacheglobal/env: 'on': hazard checking per cache line (normal mode), 'off': no hazard checking (use only for single master systems), 'cacheglobal': hazard checking globally for cache (not per cache line, testing feature, provokes more hazards than necessary), 'env' (or empty string): take value from FM_REENTRANCY_SUPPORT env var, if this is not set use 'on', default is 'env'
si0_qos_bw_regulator bool 0x0 For upstream port 0 determine if it has a BW regulator. The effect of QoS is not modelled and this parameter only alters some registers.
si1_qos_bw_regulator bool 0x0 For upstream port 1 determine if it has a BW regulator. The effect of QoS is not modelled and this parameter only alters some registers.
si2_qos_bw_regulator bool 0x0 For upstream port 2 determine if it has a BW regulator. The effect of QoS is not modelled and this parameter only alters some registers.
si3_qos_bw_regulator bool 0x0 For upstream port 3 determine if it has a BW regulator. The effect of QoS is not modelled and this parameter only alters some registers.
si4_qos_bw_regulator bool 0x0 For upstream port 4 determine if it has a BW regulator. The effect of QoS is not modelled and this parameter only alters some registers.
si5_qos_bw_regulator bool 0x0 For upstream port 5 determine if it has a BW regulator. The effect of QoS is not modelled and this parameter only alters some registers.
si6_qos_bw_regulator bool 0x0 For upstream port 6 determine if it has a BW regulator. The effect of QoS is not modelled and this parameter only alters some registers.
si_system_coherency_interface int 0x0 This parameter tells the interconnect which upstream ports should be controlled by the System Coherency Interface. Each bit corresponds to an upstream port, bit 0 to upstream port 0, etc. If the SCI port is connected but si_system_coherency_interface disable its use then messages from the upstream will be ignored and software must manage the upstream system's entrance and exit of the coherency domain.
spiden bool 0x1 Secure invasive debug enable. If both SPIDEN and DBGEN are high, enables the counting of both Non-secure and Secure events.
spniden bool 0x1 Whether secure and non-secure events are allowed to be counted in the performance monitor
version string "" The version of the interconnect. Allowed versions are:- r0p0, r1p0
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