3.4.33 ARMCortexM33CT

ARMCortexM33CT CPU component. This model is written in C++.

ARMCortexM33CT contains the following CADI targets:

  • ARM_Cortex-M33

ARMCortexM33CT contains the following MTI components:

Differences between the CT model and RTL implementations

The model does not support the following:

  • ETM, MTB, CTI, or TPIU. MTB RAM is absent on the model.
  • The power control (Q-Channel) interface.

Implementation of ITM in M-class models

This model has a parameter that enables partial support for Instrumentation Trace Macrocell (ITM). In hardware or RTL, trace data from ITM is sent in packets to the trace block serially using a single pin or wire. In the model, if it is enabled, the ITM trace data is output using an MTI trace source called ITM. The ITM trace source has an ITM_PACKET_TYPE field. The following table shows which packet types the model supports:

Table 3-158 ITM_PACKET_TYPE field values that the model supports

Field value Description Supported by model
ITM_SYNC Synchronization packet Not supported.
ITM_P_OVERFLOW Protocol: Overflow packet Not supported.
ITM_P_LOCAL_TIMESTAMP Protocol: Local timestamp packets Not supported.
ITM_P_GLOBAL_TIMESTAMP Protocol: Global timestamp packets Not supported.
ITM_P_EXTEN Protocol: Extension packet Not supported.
ITM_S_INSTRUMENTATION Source: Instrumentation packet Supported.
ITM_S_DWT_EVENT_COUNTER Hardware source: Event counter wrapping Not supported.
ITM_S_DWT_EXCEPTION Hardware source: Exception tracing Supported.
ITM_S_DWT_PC_SAMPLING Hardware source: PC sampling Not supported.
ITM_S_DWT_DATA_PC_TRACE Hardware source: DWT Data trace PC value Supported.
ITM_S_DWT_DATA_ADDRESS_TRACE Hardware source: DWT Data trace address value Supported.
ITM_S_DWT_DATA_DATA_TRACE Hardware source: DWT Data trace DATA value Supported.

Table 3-159 Ports

Name Protocol Type Description
ahbd PVBus Slave Debug AHB - core bus slave driven by the DAP.
auxfault Value Slave This is wired to the Auxiliary Fault Status Register.
bigend Signal Slave Configure big endian data format.
clk_in ClockSignal Slave The clock signal connected to the clk_in port is used to determine the rate at which the core executes instructions. Referred to in some documents as 'CLKIN'.
coproc_bus CoprocBusProtocol Slave Co-Processor Interface
cpuwait Signal Slave Stall the CPU out of reset
currns Signal Master Current Security state of the processor
currpri Value Master Current execution priority.
dbgen Signal Slave Invasive debug enable
dbgrestart Signal Slave Request for synchronised exit from halt mode
dbgrestarted Signal Master Handshakes with DBGRESTART
edbgrq Signal Slave External request to enter halt mode
event Signal Peer This peer port of event input (and output) is for wakeup from WFE and corresponds to the RTL TXEV and RXEV signals.
fpxxc Value Master Port which sends the value of the FPXXC cumulative exception flags.
halted Signal Master Indicates that the processor is in halt mode
idau PVBus Master The core will generate IDAU requests on this port.
idau_invalidate_region Value_64 Slave 64 bit number to invalid IDAU memory ranage (start_address<<32|end_address)
initnsvtor Value Slave Reset configuration port - Non-Secure Vector table offset (VTOR.TBLOFF[31:7]) out of reset This port remains functional no matter ARMv8-M Security Extensions are included or not When ARMv8-M Security Extensions are not included, all exceptions will use NS vector base address given by this port.
initsvtor Value Slave Reset configuration port - Secure Vector table offset (VTOR.TBLOFF[31:7]) out of reset It becomes functional when ARMv8-M Security Extensions are included When ARMv8-M Security Extensions are not included, this port will be ignored.
intnum Value Master Exception number of the current execution context (from IPSR[8:0]) When the processor is in Thread mode, INTNUM is 0 When the processor is in Handler mode, INTNUM is the exception number of the currently-executing exception.
irq[480] Signal Slave This signal array delivers signals to the NVIC.
locknsmpu Signal Slave Disable writes to the Non-Secure MPU_*_NS registers
locknsvtor Signal Slave Cortex-M33-specific LOCKNSVTOR, LOCKSVTAIRCR, LOCKSMPU, LOCKNSMPU, LOCKSAU. Disable writes to VTOR_NS
locksau Signal Slave Disable writes to the SAU_* registers
locksmpu Signal Slave Disable writes to the Secure MPU_* registers
locksvtaircr Signal Slave Disable writes to VTOR_S, AIRCR.PRIS, AIRCR.BFHFNMINS
lockup Signal Master Asserted when the processor is in lockup state.
niden Signal Slave Non-invasive debug enable
nmi Signal Slave Configure non maskable interrupt.
poreset Signal Slave Raising this signal will do a power-on reset of the core.
pv_ppbus_m PVBus Master The core will generate External Private Peripheral Bus requests on this port.
pvbus_m PVBus Master The core will generate bus requests on this port.
sleepdeep Signal Master Asserted when the processor is in deep sleep.
sleeping Signal Master Asserted when the processor is in sleep.
spiden Signal Slave Secure invasive debug enable
spniden Signal Slave Secure non-invasive debug enable
stcalib[2] Value Slave This is the calibration value for the SysTick timer.
stclk ClockSignal Slave This is the reference clock for the SysTick timer.
sysreset Signal Slave Raising this signal will put the core into reset mode (but does not reset the debug logic).
sysresetreq Signal Master Asserted to indicate that a reset is required.
ticks InstructionCount Master Port allowing the number of instructions since startup to be read from the CPU.
wicenack Signal Master Acknowledge signal for WICENREQ
wicenreq Signal Slave Request for deep sleep to be WIC-based deep sleep.
wicsense[483] Signal Master Indicates which input events can cause the WIC to generate the WAKEUP signal.

Table 3-160 Parameters for ARM_Cortex-M33

Name Type Default value Description
BIGENDINIT bool 0x0 Initialize processor to big endian mode
CPIF bool 0x1 Specifies whether the external coprocessor interface is included
CPNSPRESENT int 0xff Bit N means external coprocessor N (CP7:CP0) is accessible in Non-Secure state
CPSPRESENT int 0xff Bit N means external coprocessor N (CP7:CP0) is accessible in Secure state
DBGLVL int 0x2 0: Minimal debug; 1: 2 Watchpoints, 4 Breakpoint comparators; 2: 4 Watchpoints, 8 Breakpoint comparators
DSP bool 0x1 Set whether the model has the DSP extension
FPU bool 0x1 Set whether the model has VFP support
INITNSVTOR int 0x0 Non-Secure vector-table offset at reset
INITSVTOR int 0x0 Secure vector-table offset at reset
IRQDIS0 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+0]
IRQDIS1 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+32]
IRQDIS10 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+320]
IRQDIS11 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+352]
IRQDIS12 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+384]
IRQDIS13 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+416]
IRQDIS14 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+448]
IRQDIS2 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+64]
IRQDIS3 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+96]
IRQDIS4 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+128]
IRQDIS5 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+160]
IRQDIS6 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+192]
IRQDIS7 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+224]
IRQDIS8 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+256]
IRQDIS9 int 0x0 IRQ line disable mask. Bit n of this 32-bit parameter disables IRQ[n+288]
IRQLVL int 0x3 Number of bits of interrupt priority
ITM bool 0x1 Level of instrumentation trace supported. false : No ITM trace included, true: ITM trace included
LOCK_NS_MPU bool 0x0 Lock down of Non-Secure MPU registers write
LOCK_SAU bool 0x0 Lock down of SAU registers write
LOCK_S_MPU bool 0x0 Lock down of Secure MPU registers write
MPU_NS int 0x8 Number of regions in the Non-Secure MPU. If Security Extentions are absent, this is the total number of MPU regions
MPU_S int 0x8 Number of regions in the Secure MPU. If Security Extentions are absent, this is ignored
NUMIRQ int 0x20 Number of user interrupts
SAU int 0x4 Number of SAU regions (0 => no SAU)
SAU_CTRL.ALLNS bool 0x0 At reset, the SAU treats entire memory space as NS when the SAU is disabled if this is set
SAU_CTRL.ENABLE bool 0x0 Enable SAU at reset
SAU_REGION0.BADDR int 0x0 Base address of SAU region0 at reset
SAU_REGION0.ENABLE bool 0x0 Enable SAU region0 at reset
SAU_REGION0.LADDR int 0x0 Limit address of SAU region0 at reset
SAU_REGION0.NSC bool 0x0 Set NSC for SAU region0 at reset
SAU_REGION1.BADDR int 0x0 Base address of SAU region1 at reset
SAU_REGION1.ENABLE bool 0x0 Enable SAU region1 at reset
SAU_REGION1.LADDR int 0x0 Limit address of SAU region1 at reset
SAU_REGION1.NSC bool 0x0 Set NSC for SAU region1 at reset
SAU_REGION2.BADDR int 0x0 Base address of SAU region2 at reset
SAU_REGION2.ENABLE bool 0x0 Enable SAU region2 at reset
SAU_REGION2.LADDR int 0x0 Limit address of SAU region2 at reset
SAU_REGION2.NSC bool 0x0 Set NSC for SAU region2 at reset
SAU_REGION3.BADDR int 0x0 Base address of SAU region3 at reset
SAU_REGION3.ENABLE bool 0x0 Enable SAU region3 at reset
SAU_REGION3.LADDR int 0x0 Limit address of SAU region3 at reset
SAU_REGION3.NSC bool 0x0 Set NSC for SAU region3 at reset
SAU_REGION4.BADDR int 0x0 Base address of SAU region4 at reset
SAU_REGION4.ENABLE bool 0x0 Enable SAU region4 at reset
SAU_REGION4.LADDR int 0x0 Limit address of SAU region4 at reset
SAU_REGION4.NSC bool 0x0 Set NSC for SAU region4 at reset
SAU_REGION5.BADDR int 0x0 Base address of SAU region5 at reset
SAU_REGION5.ENABLE bool 0x0 Enable SAU region5 at reset
SAU_REGION5.LADDR int 0x0 Limit address of SAU region5 at reset
SAU_REGION5.NSC bool 0x0 Set NSC for SAU region5 at reset
SAU_REGION6.BADDR int 0x0 Base address of SAU region6 at reset
SAU_REGION6.ENABLE bool 0x0 Enable SAU region6 at reset
SAU_REGION6.LADDR int 0x0 Limit address of SAU region6 at reset
SAU_REGION6.NSC bool 0x0 Set NSC for SAU region6 at reset
SAU_REGION7.BADDR int 0x0 Base address of SAU region7 at reset
SAU_REGION7.ENABLE bool 0x0 Enable SAU region7 at reset
SAU_REGION7.LADDR int 0x0 Limit address of SAU region7 at reset
SAU_REGION7.NSC bool 0x0 Set NSC for SAU region7 at reset
SECEXT bool 0x1 Whether the ARMv8-M Security Extensions are included
WIC bool 0x1 Include support for WIC-mode deep sleep
WICLINES int 0x23 Number of lines supported by the WIC interface
cpi_div int 0x1 divider for calculating CPI (Cycles Per Instruction)
cpi_mul int 0x1 multiplier for calculating CPI (Cycles Per Instruction)
ignore-SCR.SLEEPONEXIT bool 0x0 Never sleep on exit from handler to thread mode.
master_id int 0x0 Master ID presented in bus transactions
min_sync_level int 0x0 force minimum syncLevel (0=off=default,1=syncState,2=postInsnIO,3=postInsnAll)
scheduler_mode int 0x0 Control the interleaving of instructions in this processor (0=default long quantum, 1=low latency mode, short quantum and signal checking, 2=lock-breaking mode, long quantum with additional context switches near load-exclusive instructions, 3=ISSCompare)
semihosting-Thumb_SVC int 0xab T32 SVC number for semihosting
semihosting-cmd_line string "" Command line available to semihosting SVC calls
semihosting-cwd string "" Base directory for semihosting file access.
semihosting-enable bool 0x1 Enable semihosting SVC traps. Applications that do not use semihosting must set this parameter to false.
semihosting-heap_base int 0x0 Virtual address of heap base
semihosting-heap_limit int 0x10700000 Virtual address of top of heap
semihosting-prefix bool 0x0 Prefix semihosting output with target instance name
semihosting-stack_base int 0x10700000 Virtual address of base of descending stack
semihosting-stack_limit int 0x10800000 Virtual address of stack limit
vfp-enable_at_reset bool 0x0 Enable VFP in CPACR, CPPWR, NSACR at reset. Warning: Arm recommends going through the implementation's suggested VFP power-up sequence!
write_unknown_regs_at_exception bool 0x0 DEPRECATED and non-functional in device models.
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