3.10.49 PL330_DMAC

ARM PrimeCell DMA Controller(PL330). This model is written in LISA+.

PL330_DMAC contains the following CADI targets:

  • ClockTimerThread
  • ClockTimerThread64
  • PL330_DMAC
  • SchedulerThread
  • SchedulerThreadEvent

PL330_DMAC contains the following MTI components:

PL330_DMAC - about

The model uses a single LISA+ component but with a C++ model for each of the channels included in the LISA+ file. Enabled channels are kept on an enabled_channels stack in priority order. When a channel state changes, re-arbitration takes place to make the highest (topmost) channel active.

Transaction labels

Each transaction carries the identity of the requesting thread. This controller has up to eight channel threads and a manager thread. Each has an ID. In the hardware, the ID is AxID[3:0], with 0x0 - (number of channels – 1) identifying channels and (number of channels) identifying the manager: for example, 0x0-0x7 and 0x8, respectively. The manager originates only instruction fetches, and the manager ID is also used for instruction fetches issued by the channels.

In the model, the identity of the requesting thread is encoded into each transaction using the low-order 16 bits of the Master ID field:

  • Channel data: 0-7.
  • Channel instruction fetch: 0xffff.
  • Manager instruction fetch: 0xffff.

If a downstream component needs to know the IDs of bus masters that use either the low-order 16 bits or the label, use the label. The LabellerForDMA330 component shifts the low-order 16 bits into the label, while providing a degree of control over the label encoding. The example below maintains separate IDs for each data channel while using the correct hardware ID to identify instruction fetch for a DMA-330 with 8 channels:

pl330_dma : PL330_DMAC( "p_max_channels" = 8 );
dma_labeller : LabellerForDMA330(
    "dma330_discriminate_data_channels" = true,
    "dma330_s_instruction_label" = 8,
    "dma330_ns_instruction_label" = 8 );
pl330_dma.pvbus_m => dma_labeller.pvbus_s;
dma_labeller.pvbus_m => output_bus.pvbus_s;

Table 3-375 Ports

Name Protocol Type Description
clk_in ClockSignal Slave Clock input.
irq_abort_master_port Signal Master Undefined instruction or instruction error.
irq_master_port[32] Signal Master Sets when DMASEV.
pvbus_m PVBus Master Master port for all memory accesses.
pvbus_s PVBus Slave Slave port for all register accesses (secure).
pvbus_s_ns PVBus Slave Slave port for all register accesses (non-secure).
reset_in Signal Slave System reset.

Table 3-376 Parameters for PL330_DMAC

Name Type Default value Description
activate_delay int 0x0 request delay
fifo_size int 0x10 Channel FIFO size in bytes
generate_clear bool 0x0 Generate clear response
max_transfer int 0x100 Largest atomic transfer
p_axi_bus_width_param int 0x20 AXI bus width
p_buffer_depth int 0x10 buffer depth
p_cache_line_words int 0x1 number of words in a cache line
p_cache_lines int 0x1 number of cache lines
p_controller_boots bool 0x1 DMA boots from reset
p_controller_nsecure bool 0x0 Controller non-secure at reset (boot_manager_ns)
p_irq_nsecure int 0x0 Interrupts non-secure at reset
p_lsq_read_size int 0x4 LSQ read buffer depth
p_lsq_write_size int 0x4 LSQ write buffer depth
p_max_channels int 0x8 virtual channels
p_max_irqs int 0x20 number of interrupts
p_max_periph int 0x20 number of peripheral interfaces
p_perip_request_acceptance_0 int 0x2 Peripheral 0 request acceptance
p_perip_request_acceptance_1 int 0x2 Peripheral 1 request acceptance
p_perip_request_acceptance_10 int 0x2 Peripheral 10 request acceptance
p_perip_request_acceptance_11 int 0x2 Peripheral 11 request acceptance
p_perip_request_acceptance_12 int 0x2 Peripheral 12 request acceptance
p_perip_request_acceptance_13 int 0x2 Peripheral 13 request acceptance
p_perip_request_acceptance_14 int 0x2 Peripheral 14 request acceptance
p_perip_request_acceptance_15 int 0x2 Peripheral 15 request acceptance
p_perip_request_acceptance_16 int 0x2 Peripheral 16 request acceptance
p_perip_request_acceptance_17 int 0x2 Peripheral 17 request acceptance
p_perip_request_acceptance_18 int 0x2 Peripheral 18 request acceptance
p_perip_request_acceptance_19 int 0x2 Peripheral 19 request acceptance
p_perip_request_acceptance_2 int 0x2 Peripheral 2 request acceptance
p_perip_request_acceptance_20 int 0x2 Peripheral 20 request acceptance
p_perip_request_acceptance_21 int 0x2 Peripheral 21 request acceptance
p_perip_request_acceptance_22 int 0x2 Peripheral 22 request acceptance
p_perip_request_acceptance_23 int 0x2 Peripheral 23 request acceptance
p_perip_request_acceptance_24 int 0x2 Peripheral 24 request acceptance
p_perip_request_acceptance_25 int 0x2 Peripheral 25 request acceptance
p_perip_request_acceptance_26 int 0x2 Peripheral 26 request acceptance
p_perip_request_acceptance_27 int 0x2 Peripheral 27 request acceptance
p_perip_request_acceptance_28 int 0x2 Peripheral 28 request acceptance
p_perip_request_acceptance_29 int 0x2 Peripheral 29 request acceptance
p_perip_request_acceptance_3 int 0x2 Peripheral 3 request acceptance
p_perip_request_acceptance_30 int 0x2 Peripheral 30 request acceptance
p_perip_request_acceptance_31 int 0x2 Peripheral 31 request acceptance
p_perip_request_acceptance_4 int 0x2 Peripheral 4 request acceptance
p_perip_request_acceptance_5 int 0x2 Peripheral 5 request acceptance
p_perip_request_acceptance_6 int 0x2 Peripheral 6 request acceptance
p_perip_request_acceptance_7 int 0x2 Peripheral 7 request acceptance
p_perip_request_acceptance_8 int 0x2 Peripheral 8 request acceptance
p_perip_request_acceptance_9 int 0x2 Peripheral 9 request acceptance
p_periph_nsecure bool 0x0 Peripherals non-secure at reset
p_read_issuing_capability int 0x1 AXI read issuing capability
p_reset_pc int 0x60000000 DMA PC at reset
p_write_issuing_capability int 0x1 AXI write issuing capability
revision string "r0p0" revision ID
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