3.10.62 SP810_SysCtrl

PrimeXsys System Controller(SP810) NB: Only EB relevant functionalities are fully implemented. This model is written in LISA+.

SP810_SysCtrl contains the following CADI targets:

  • ClockDivider
  • SP810_SysCtrl

SP810_SysCtrl contains the following MTI components:

Table 3-398 Ports

Name Protocol Type Description
clk_in ClockSignal Slave Clock input.
hclkdivsel ValueState Master Define the processor clock/bus clock ratio. Not fully implemented. Using this port has unpredictable results.
npor Signal Slave Power on reset. Not fully implemented. Using this port has unpredictable results.
pll_en Signal Master PLL enable output. Not fully implemented. Using this port has unpredictable results.
pvbus PVBus Slave Slave port for register access.
ref_clk_in ClockSignal Slave Clock source used by the Timer and Watchdog modules.
remap_clear StateSignal Master Remap clear request output.
remap_stat StateSignal Slave Remap status input. Not fully implemented. Using this port has unpredictable results.
sleep_mode Signal Master Control clocks for SLEEP mode. Not fully implemented. Using this port has unpredictable results.
sys_id ValueState Slave Unused port.
sys_mode ValueState Slave Present system mode. Not fully implemented. Using this port has unpredictable results.
sys_stat ValueState Slave System status input. Not fully implemented. Using this port has unpredictable results.
timer_clk_en[4] ClockRateControl Master Timer clock enable n.
wd_clk_en Signal Master Watchdog module clock enable output. Not fully implemented. Using this port has unpredictable results.
wd_en Signal Slave Watchdog module enable input. Not fully implemented. Using this port has unpredictable results.

Table 3-399 Parameters for SP810_SysCtrl

Name Type Default value Description
sysid int 0x0 System Identification Register.
use_s8 bool 0x0 Use Switch 8 (S1-S4)
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