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3.10.61 SP805_Watchdog

ARM Watchdog Module(SP805). This model is written in LISA+.

SP805_Watchdog contains the following CADI targets:

  • SP805_Watchdog

SP805_Watchdog contains the following MTI components:

Table 3-396 Ports

Name Protocol Type Description
clk_in ClockSignal Slave Clock input, typically 1MHz, driving master count rate.
irq_out Signal Master Interrupt signaling.
pvbus_s PVBus Slave Slave port for register access.
reset_in Signal Slave Reset signaling.
reset_out Signal Master Reset signaling.

Table 3-397 Parameters for SP805_Watchdog

Name Type Default value Description
simhalt bool 0x0 Halt on reset.
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