3.7.16 IntelStrataFlashJ3

Intel Strata Flash J3 LISA+ model. This model is written in LISA+.

IntelStrataFlashJ3 contains the following CADI targets:

  • IntelStrataFlashJ3

IntelStrataFlashJ3 contains the following MTI components:

IntelStrataFlashJ3 - about

This component is an efficient implementation of a NOR Flash memory type device, an Intel StrataFlash Memory (J3).

In normal usage, the device acts as Read Only Memory (ROM) whose contents can be determined either by programming using the flashloader port or by using standard flash programming software running on the model, such as the ARM® Firmware Suite.

The implementation of this component is approximately that of the Intel part in the VE development board. The component is effectively organized as a bank of two 16-bit Intel Flash components forming a 32-bit component that can be read or programmed in parallel. The component supports all hardware behavior except for:

  • Protection register.
  • Enhanced configuration register.
  • Unique device identifier.
  • One time programmable cells.
  • Suspend/resume, which is silently ignored.
  • Status interrupt line.

All block operations are atomic. This means that the status register state machine status bit always reads 1, ready.

In normal operation, this component has no user-visible registers, but you can read from it as if it is memory.

Programming it or changing the configuration requires a sequence of special write operations: see general flash programming documentation. The component supports Common Flash Interface query operations, which allow drivers to determine the properties of the flash memory.

Note:

The model interprets all writes as requests to the programming state machine, and there are many state-machine states that do not support subsequent reads and return 0xdeaddead for them. Therefore, when simulating a ROM, use the trapwrite=true option.

Debug features

Use the diagnostics parameter to select the level of diagnostic output:

Level 0
None.
Level 1

Report probable driver error operations:

  • Unaligned operations that fault.
  • Accesses that the state machine does not expect.
  • Transitions of the state machine to unknown states.
  • Writes to locked blocks and illegal lock commands.
Level 2

Report unimplemented and therefore ignored operations, and log lock commands.

Level 3
Warn if a flash write attempts to set bits (the write works if unphysical_writes=true).
Level 4
Log every read and write.

Table 3-232 Ports

Name Protocol Type Description
flashloader FlashLoaderPort Slave Can be used to load code/data into the flash.
mbs_control PVBusSlaveControl Master This is an internal control that is used to control the encapsulated PVBusSlave.
mem_port PVDevice Slave PVDevice port that is connect PVBusSlave port.
pvbus PVBus Slave This is where the address and the data comes from the bus.

Table 3-233 Parameters for IntelStrataFlashJ3

Name Type Default value Description
diagnostics int 0x0 Diagnostic level
model_blocklock bool 0x0 Model per-block locking
size int 0x40000 Memory Size
trapwrite bool 0x0 Generate abort on write
unphysical_writes bool 0x1 Writes to flash are overwrite not AND
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