5.15.13 Memory bus trace

If enabled, this source traces transactions that are initiated through the memory bus master port of the processor. These accesses use physical addresses.

Output syntax:

<time> <scale> {<cpu>} B<rw><sz><fd><lk><p><s> I<wrcbs> O<wrcbs> <master_id> <addr> <data>

<time>

Timestamp (decimal value).

<scale>

Unit for <time>. This element gives consistency with device-specific Tarmac Trace formats.

<cpu>

Processor, or other component, that gave the instruction.

<rw>
R
Read access.
W
Write access.
<sz>

Size of the data transfer in bytes.

<fd>
I
Opcode fetch.
D
Data load/store or an MMU access.
<lk>
L
Locked access.
X
Exclusive access.
_, underscore
Normal access.
<p>
P
Privileged access.
_, underscore
Normal access.
<s>
S
Secure access.
N
Non-secure access.
I<wrcbs>

Inner cache attributes. See O<wrcbs>.

O<wrcbs>

Outer cache attributes:

<w>
W
Allocate on write.
_, underscore
No allocate on write.
<r>
R
Allocate on read.
_, underscore
No allocate on read.
<c>
C
Cacheable access.
_, underscore
Non-cacheable access.
<b>
B
Bufferable access.
_, underscore
Non-bufferable access.
<s>
S
Shareability access.
_, underscore
Non-shareability access.
<master_id>

Master ID of the transaction.

<addr>

Physical address that is used to access memory, in hexadecimal format.

<data>

Hexadecimal value of data transferred. The data padding is according to the size of the transfer. Byte ordering is from lowest to highest byte. This ordering means that for accesses in little endian mode, the data occurs mirrored compared to the register/memory access records.

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