The GICv3 architecture defines two parts: the core interface (integrated into the core) and the Interrupt Redistribution Infrastructure (IRI). You can configure all ARMv8-A cores to include a GICv3 interface. You can integrate a separate GICv3IRI component into your platforms. Communication between the core and the IRI is over an architected packet interface. An internal communication protocol represents the packets that pass over this interface.

You can configure the GICv3 models in some platforms to act as though they were GICv2 or GICv2-M models. Even in this mode, you need a GICv3IRI component and supported core. Configure them to comply with the same standard.

• Support of the GITS_CTLR.Quiesce bit is not complete.
• Support of ITS save/restore is not complete. Configuration stays within the model and it does not use allocated memory.
• GICD_CTLR.RWP does not perform adequately. This difference is only an issue if you use the distributor in systems with delaying interface between the distributor and the cores. DO NOT use this version of the model for simulation of the GIC in a setup where interfaces are not instantly reactive.
• Set the environment variable FASTSIM_GIC_MEMORY_MAP to 1 so the memory map of certain models that are included in the platform being run will be printed to stderr. This functionality is available for all GICv3 and later models.

In addition to requiring the presence of an ITS that is configured as shown in 3.10.24 GICv3IRI, GICv4 requires you to enable the virtual LPIs feature and to configure a virtual PE table using the parameters shown in the following example:

    "virtual-lpi-support"=true, 
    "GITS_BASER4-type"=2 //Type 2 is Virtual PEs. 
                         //Such a table is needed for GICv4 functionality.