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This section describes the model of the GICv3.
The PV models implement the Generic Interrupt Controller architecture version 3 (GICv3).
The GICv3 architecture defines two parts: the core interface (integrated into the core) and the Interrupt Redistribution Infrastructure (IRI). You can configure all ARMv8-A cores to include a GICv3 interface. You can integrate a separate GICv3IRI component into your platforms. Communication between the core and the IRI is over an architected packet interface. An internal communication protocol represents the packets that pass over this interface.
You can configure the GICv3 models in some platforms to act as though they were GICv2 or GICv2-M models. Even in this mode, you need a GICv3IRI component and supported core. Configure them to comply with the same standard.
Some features differ in the model.
FASTSIM_GIC_MEMORY_MAPto 1 so the memory map of certain models that are included in the platform being run will be printed to
stderr. This functionality is available for all GICv3 and later models.
GICv4 is an extension of the GICv3 architecture. It allows the direct injection of LPIs into a virtualized system through the
virtual-lpi-support parameter of the
In addition to requiring the presence of an ITS that is configured as shown in 3.10.24 GICv3IRI, GICv4 requires you to enable the virtual LPIs feature and to configure a virtual PE table using the parameters shown in the following example:
"virtual-lpi-support"=true, "GITS_BASER4-type"=2 //Type 2 is Virtual PEs. //Such a table is needed for GICv4 functionality.