1.4.1 Caches in PV models

Some processor models have PV-accurate caches, but others do not model Level 1 or Level 2 caches.

Cores that have PV-accurate cache implementation provide a functionally-accurate model. For more information, see the processor component descriptions.

Other PV models do not model Level 1 or Level 2 caches. The system coprocessor registers related to cache operations permit cache aware software to work, but in most cases they only check register access permissions.

The registers affected on all code translation processor models are:

  • Invalidate and/or Clean Entire ICache/DCache.
  • Invalidate and/or Clean ICache/DCache by MVA.
  • Invalidate and/or Clean ICache/DCache by Index.
  • Invalidate and/or Clean Both Caches.
  • Cache Dirty Status.
  • Data Write Barrier.
  • Data Memory Barrier.
  • Prefetch ICache Line.
  • ICache/DCache lockdown.
  • ICache/DCache master valid.

Functional caches in Fast Models - about

Fast Models implement two types of cache model: register model and functional model.

A register model provides all the cache control registers so that cache operations succeed, but does not model the state of the cache. All accesses go to memory.

A functional model tracks cache state and its contents at each level of the memory hierarchy. Incorrect cache management might return incorrect data, as it would on real hardware.

Fast Models provide:

  • System IPs that support caches.
  • Register models of caches on all processors that support caches and also the PL310 cache controller (PL310_L2CC).
  • Functional models of caches integrated into Cortex cores.

For a core with no L2 cache, the configuration parameters are:

icache-state-modelled
Set whether the I-cache has stateful implementation.
dcache-state-modelled
Set whether the D-cache has stateful implementation.

For Arm®v7‑A cores with an L2 cache, the configuration parameters are:

l1_icache-state-modelled
Set whether L1 I-cache has stateful implementation.
l1_dcache-state-modelled
Set whether L1 D-cache has stateful implementation.
l2_cache-state-modelled
Enable unified Level 2 cache state model.

For Armv8‑A cores with an L2 cache, the configuration parameters are:

icache-state_modelled
Set whether L1 I-cache has stateful implementation. Instructions at L2 or L3 are not cached in Fast Models.
dcache-state_modelled
Set whether D-cache has stateful implementation at L1, L2, and L3.

Functional caches in Fast Models - performance

Enabling functional cache modeling is likely to reduce performance.

Enable the L1 and L2 functional caches together. For consistent system operation, ARM recommends that you either disable functional behavior completely or enable it for both I and D L1 caches and the L2 cache.

Cache enablement must be system wide. If you enable cache state modeling in any component then you must enable it in all components in the system, including all cores (L1 and L2) and any external cache controller (such as the PL310_L2CC) and any interconnect that has caches.

If platform memory is being modeled outside of the Fast Models environment, for example in a SystemC environment, use of functional cache modeling might improve performance if there is no other fast route to memory.

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