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A bus system consists of a number of bus masters, some infrastructure and a number of bus slaves.
Each bus master must contain a
PVBusMaster subcomponent, and each bus slave must contain a
PVBusSlave subcomponent. These subcomponents provide
PVBus master and slave ports. Each
PVBus master port can only connect to one slave, but any number of other masters can connect to the same slave.
PVBusSlave components communicate using the
PVBusDecoder components can be added to the bus system. Each of these permits its masters to connect to multiple slaves, each associated with a different bus address range.
PVBusSlave subcomponents provide built-in support for declaring memory-like, device-like, abort or ignore address ranges.
PVBus has support for dealing efficiently with memory-like devices such as RAM, ROM, and Flash.
All communication over the
PVBus is performed using transactions that are generated by
PVBusMaster subcomponents and fulfilled by
PVBusSlave components. Transactions have a 32-bit Master ID, which is the ID of the bus master. Transactions can be routed to the slave device through its
PVBusSlave subcomponent. When configured, the
PVBusSlave can handle memory-like transactions efficiently without having to route these transactions to the slave device. Transactions are atomic unless slave devices block transactions, for example an SMMU with stall mode enabled. A slave device that can block transactions and all its upstream bus components must be re-entrant safe for bus transactions.
Fast Models provides some example