Non-Confidential | ![]() | 100964_1180_00_en | ||
| ||||
Home > Versatile Express Model > VE - components > VE_SysRegs component |
This section describes the VE system registers component.
This LISA+ component is a model of the VE status and system control registers.
This section describes the ports.
Table 9-15 VE_SysRegs ports
Name | Protocol | Type | Description |
---|---|---|---|
cb[0-1] |
VECBProtocol |
Master | The Configuration Bus (CB) controls the power and reset sequence. |
clock_24Mhz |
ClockSignal |
Slave | Reference clock for internal counter register. |
clock_100Hz |
ClockSignal |
Slave | Reference clock for internal counter register. |
clock_CLCD |
ClockRateControl |
Master | The clock for the LCD controller. |
lcd |
LCD |
Master | Multimedia bus interface output to the LCD. |
leds |
ValueState |
Master | Displays state of the SYS_LED register using the eight colored LEDs on the status bar. |
mmb[0-2] |
LCD |
Slave | Multimedia bus interface input. |
mmc_card_present |
StateSignal |
Slave | Indicates the presence of a MultiMedia Card (MMC) image. |
pvbus |
PVBus |
Slave | Slave port for connection to PV bus master/decoder. |
system_reset |
Signal |
Master | Signal to the platform a complete system reset. Writes to the System Configuration registers can trigger the reset signal. |
user_switches |
ValueState |
Master | Provides state for the eight User DIP switches on the left side of the CLCD status bar, equivalent to switch S6 on VE hardware. |
This section describes the parameters.
Table 9-16 VE_SysRegs parameters
Name | Type | Default value | Description |
---|---|---|---|
exit_on_shutdown |
bool |
false |
Used to shut down the system. When true , if software uses the SYS_CFGCTRL
function SYS_CFG_SHUTDOWN , then the simulator shuts
down and exits.a |
mmbSiteDefault |
int |
|
Default MultiMedia Bus (MMB) source (0=motherboard, 1=daughterboard 1, 2=daughterboard 2). |
sys_proc_id0 |
int |
|
Processor ID register at CoreTile Express Site 1. |
sys_proc_id1 |
int |
|
Processor ID at CoreTile Express Site 2. |
tilePresent |
bool |
true |
Tile fitted. |
user_switches_value |
int |
0 |
User switches. |
This section describes the configuration registers.
Table 9-17 VE_SysRegs registers
Name | Offset | Access | Description |
---|---|---|---|
SYS_ID |
|
Read/write | System identity. |
SYS_SW |
|
Read/write | Bits[7:0] map to switch S6. |
SYS_LED |
|
Read/write | Bits[7:0] map to user LEDs. |
SYS_100HZ |
|
Read only | 100Hz counter. |
SYS_FLAGS |
|
Read/write | General purpose flags. |
SYS_FLAGSCLR |
|
Write only | Clear bits in general purpose flags. |
SYS_NVFLAGS |
|
Read/write | General purpose non-volatile flags. |
SYS_NVFLAGSCLR |
|
Write only | Clear bits in general purpose non-volatile flags. |
SYS_MCI |
|
Read only | MCI. |
SYS_FLASH |
|
Read/write | Flash control. |
SYS_CFGSW |
|
Read/write | Boot select switch. |
SYS_24MHZ |
|
Read only | 24MHz counter. |
SYS_MISC |
|
Read/write | Miscellaneous control flags. |
SYS_DMA |
|
Read/write | DMA peripheral map. |
SYS_PROCID0 |
|
Read/write | Processor ID. |
SYS_PROCID1 |
|
Read/write | Processor ID. |
SYS_CFGDATA |
|
Read/write | Data to be read/written from/to motherboard controller. |
SYS_CFGCTRL |
|
Read/write | Control data transfer to motherboard controller. |
SYS_CFGSTAT |
|
Read/write | Status of data transfer to motherboard. |
This component was tested as part of the Versatile™ Express model.
For more information on the SYS_CFGCTRL
function values, see the Motherboard Express μATX V2M-P1 Technical Reference Manual.