See $PVLIB_HOME/examples/LISA/FVP_Base/ for LISA+ source, project files, and build scripts for the Base Platform FVPs.

The standard peripheral set enables software development and porting. The platform is an evolution of the VE Fixed Virtual Platforms (FVPs), based on the Arm^® Versatile™ Express (VE) hardware development platform.

The Base Platform system model provides:

• Two configurable clusters of up to four core models that implement:

  • AArch64 at all exception levels.
  • Configurable AArch32 support at all exception levels.
  • Configurable support for little and big endian at all exception levels.
  • Generic timers.
  • Self-hosted debug.
  • CADI debug.
  • GICv3 memory-mapped processor interfaces and distributor.
• Peripherals for multimedia or networking environments.
• Four PL011 UARTs.
• A CoreLink™ CCI-400 Cache Coherent Interconnect.
• Architectural GICv3 model.
• High Definition LCD Display Controller, 1920×1080 resolution at 60fps, with single I2S and four stereo channels.
• 64MB NOR flash and board peripherals.
• CoreLink TZC-400 TrustZone^® Address Space Controller.