LISA+ source, project files, and build scripts for the VE FVPs are available in the $PVLIB_HOME/examples/LISA/FVP_VE/ directory.
Arm produces the VE hardware development platform. The Motherboard Express μAdvanced Technology Extended (ATX) V2M-P1 is the basis for an integrated software and hardware development system. This system is also based on the Arm® Symmetric MultiProcessor (SMP) system architecture.
The VE FVPs are system models implemented in software. Each model
- A virtual implementation of the Arm VE motherboard.
- A single daughterboard containing one or more Arm processors.
- Associated interconnections.
The motherboard provides:
- Peripherals for multimedia or networking environments.
- Access to motherboard peripherals and functions through a static memory
bus to simplify access from daughterboards.
- High-performance PCI-Express slots for expansion cards.
- Consistent memory maps with different processor daughterboards that
simplify software development and porting.
- Automatic detection and configuration of attached CoreTile Express and
LogicTile Express daughterboards.
- Automatic shutdown for over-temperature or power supply failure.
- No system power-on for unconfigurable daughterboards.
- Power sequencing of system.
- Drag and drop file updating of configuration files.
- Support of either a 12V power-supply unit or an external ATX power
- Support of FPGA and processor daughterboards to provide custom
peripherals, early access to processor designs, or production test chips.
Note: Arm bases the models on the VE platform memory map, but
does not intend them to be accurate representations of a specific VE hardware revision. The
VE FVPs support selected peripherals. The models are sufficiently complete and accurate to
boot the same operating system images as the VE hardware.
VE FVPs provide functionally accurate models for software execution.
However, the models sacrifice timing accuracy to increase simulation speed. Key deviations
from hardware are:
- Approximate timing.
- Simplified buses.
- No implementations for processor caches and the related write
9-1 Top-level block diagram of a VE model