5.15.1 TarmacTrace parameters

This section describes the parameters for the TarmacTrace plug-in.

Each parameter is prefixed with TRACE.TarmacTrace, for instance:

TRACE.TarmacTrace.end-instruction-count

Table 5-16 TarmacTrace parameters

Name Type Default value Allowed values Description
end-instruction-count int 0 0 - 0x7FFFFFFFFFFFFFFF The instruction count at which to stop tracing. Default is to never stop tracing.
instruction-count-is-per-target bool true true, false If true (default) then the start-instruction-count and end-instruction-count parameters apply to individual targets separately. If false, all components start and stop tracing when the first component reaches the instruction count.
loadstore-display-width int 8 0 - 40 Memory transactions can involve up to 64 bytes. For easier readability, these transactions can be broken up into multiple memory access records with a smaller number of bytes. 0 means do not break up any transaction.
quantum-size int 0x2710 0x1 - 0x7fffffff Set the default quantum size that is used in computing when the tracing should start and stop. The CORE_INFO.QUANTUM_SIZE trace source field of the component overrides this parameter, when present.
quiet bool false true, false Limit output to trace information.
start-instruction-count int 0 0 - 0x7FFFFFFFFFFFFFFF The instruction count at which the tracing starts. Default is to trace from the beginning.
trace_aarch64_vfp_full_width bool false true, false Trace a write to an S or D register in AArch64 as a write to the corresponding V register.
trace_atomic bool true true, false Trace memory updates by atomic operations.
trace_branches bool false true, false Trace changes of the program flow like direct or indirect branches and exception returns.
trace_bte bool true true, false Trace opcodes rejected by BTE (Branch Target Enforcement) instructions.
trace_bus_accesses bool false true, false Trace bus accesses of the core, including accesses by the caches of the core. This trace slows down the model considerably.
trace_cache bool true true, false Trace cache fills and evictions.
trace_core_registers bool true true, false Trace the core registers R0-R14, the CPSR, and the SPSR.
trace_cp15 bool true true, false Trace writes to CP15 registers.
trace_dap bool true true, false Trace accesses on the debug access port.
trace_ete bool true true, false Trace packets generated by the ETE.
trace_events bool true true, false Trace events, for example exceptions and mode changes.
trace_exception_reasons bool true true, false Trace INFO_EXCEPTION_REASONS (M-class processors only).
trace-file string "" - Trace output file (stdout by default, stderr if "STDERR").
trace-file-per-comp bool false true, false Write trace to multiple files.
trace_generic_events bool false true, false Trace generic events.
trace_gicv3 bool true true, false Trace GICv3 memory-mapped accesses.
trace_gicv3_comms int 0 0 - 7 Trace GICv3 communications between cores and distributor. Bitfield:
1
Trace processor.
2
Trace RD0.
4
Trace internal.
trace_gicv3_its bool false true, false Trace GICv3 ITS command execution.
trace_gicv3_reads bool false true, false Trace GICv3 memory-mapped reads.
trace-inst-stem string "" - Base instance path to select an instance or group of instances to trace. For example:
-C TRACE.TarmacTrace.trace-inst-stem=css.cluster0.cpu3
trace_instructions bool true true, false Trace instructions.
trace_loads_store_memtype bool false true, false Show memory type information for core loads and stores.
trace_loads_stores bool true true, false Trace loads and stores that are triggered by instructions. These loads and stores might go into the memory subsystem, into a cache, or into a TCM. This trace slows down the model considerably.
trace_memory bool false true, false Trace memory accesses just outside the core.
trace_mmu bool true true, false Trace MMU tablewalks and associated information.
trace_spe bool true true, false Trace SPE data that is written to memory.
trace_tag_loads_stores bool true true, false Trace tag loads and stores that are triggered by MTE instructions. These might go into the memory subsystem, into a cache, or into a TCM. This trace slows down the model considerably.
trace_vfp bool true true, false Trace the VFP and Neon™ registers, including FPSCR and FPEXC.
unbuffered bool false true, false Trace events as they arrive, and flush each fwrite. Prints IT even when IS should be printed.
updated-registers bool false true, false Trace updated value of registers rather than the written value.
use_instr_cnt_as_timestamp bool false true, false Use the instruction count as the timestamp instead of the simulation time.
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