3.10.50 PL350_SMC

ARM PrimeCell Static Memory Controller(PL350). This model is written in LISA+.

PL350_SMC contains the following CADI targets:

  • PL350_SMC
  • PVBusExclusiveMonitor
  • TZSwitch

PL350_SMC contains the following MTI components:

PL350_SMC - about

This component provides two memory interfaces. Each interface can be connected to a maximum of four memory devices, giving a total of eight inputs from the PVBusDecoder and eight outputs to either SRAM or NAND devices. Only one kind of memory can be connected to a particular interface, either SRAM or NAND.

It provides a PVBus slave to control the device behavior. A remap port is also provided to assist in remapping particular memory regions.

Performance

This component is optimized to have negligible impact on transaction performance, except when memory remap settings are changed when there might be a significant effect.

Table 3-377 Ports

Name Protocol Type Description
apb_interface PVBus Slave This is where we expect to receive all the APB data which is used to read/write the device regs.
axi_chip_if0_in[4] PVBus Slave This is where we expect to receive all the AXI data which is used to read/wrie NAND/RAM mem.
axi_chip_if0_out[4] PVBus Master Master interface 0 to connect to SRAM/NAND.
axi_chip_if1_in[4] PVBus Slave This is where we expect to receive all the AXI data which is used to read/wrie NAND/RAM mem.
axi_chip_if1_out[4] PVBus Master Master interface 1 to connect to SRAM/NAND.
axi_remap PVBus Slave This is the remap port that the designer needs to connect to zero.
irq_in_if0 Signal Slave Interrupt signals from devices connected on interface 0.
irq_in_if1 Signal Slave Interrupt signals from device connected on interface 1.
irq_out Signal Master Interrupt port.
nand_remap_port PVBus Slave Remaps the connected NAND port to 0x0.

Table 3-378 Parameters for PVBusExclusiveMonitor

Name Type Default value Description
apply_access_width_criteria_to_non_excl_stores bool 0x1 Apply the given exclusive store width matching criteria to non-exclusive stores
clear_on_strex_address_mismatch bool 0x1 Whether monitor is cleared when strex fails due to address mismatch
enable_component bool 0x1 Enable component
log2_granule_size int 0x0 log2 of address granule size
match_access_width bool 0x0 Fail STREX if not the same access width as LDREX
match_secure_state bool 0x1 Treat the secure state like an address bit
monitor_non_excl_stores bool 0x0 Monitor non-exclusive stores from the same master
number_of_monitors int 0x8 Number of monitors
shareability_domain int 0x3 Maximum shareability domain of interest, transactions outside of the domain will pass through un-monitored (0-non-shared, 1-inner, 2-outer, 3-system)

Table 3-379 Parameters for TZSwitch

Name Type Default value Description
normal int 0x2 Normal Port
secure int 0x1 Secure Port

Table 3-380 Parameters for PL350_SMC

Name Type Default value Description
IF0_CHIP0 bool 0x0 Interface 0 chip 0 connected
IF0_CHIP0_BASE int 0x0 Interface 0 chip 0 Base address
IF0_CHIP0_SIZE int 0x0 Interface 0 chip 0 Size
IF0_CHIP1 bool 0x0 Interface 0 chip 1 connected
IF0_CHIP1_BASE int 0x0 Interface 0 chip 1 Base address
IF0_CHIP1_SIZE int 0x0 Interface 0 chip 1 Size
IF0_CHIP2 bool 0x0 Interface 0 chip 2 connected
IF0_CHIP2_BASE int 0x0 Interface 0 chip 2 Base address
IF0_CHIP2_SIZE int 0x0 Interface 0 chip 2 Size
IF0_CHIP3 bool 0x0 Interface 0 chip 3 connected
IF0_CHIP3_BASE int 0x0 Interface 0 chip 3 Base address
IF0_CHIP3_SIZE int 0x0 Interface 0 chip 3 Size
IF0_MEM_TYPE_PARAMETER int 0x0 Interface 0 Mem type
IF1_CHIP0 bool 0x0 Interface 1 chip 0 connected
IF1_CHIP0_BASE int 0x0 Interface 1 chip 0 Base address
IF1_CHIP0_SIZE int 0x0 Interface 1 chip 0 Size
IF1_CHIP1 bool 0x0 Interface 1 chip 1 connected
IF1_CHIP1_BASE int 0x0 Interface 1 chip 1 Base address
IF1_CHIP1_SIZE int 0x0 Interface 1 chip 1 Size
IF1_CHIP2 bool 0x0 Interface 1 chip 2 connected
IF1_CHIP2_BASE int 0x0 Interface 1 chip 2 Base address
IF1_CHIP2_SIZE int 0x0 Interface 1 chip 2 Size
IF1_CHIP3 bool 0x0 Interface 1 chip 3 connected
IF1_CHIP3_BASE int 0x0 Interface 1 chip 3 Base address
IF1_CHIP3_SIZE int 0x0 Interface 1 chip 3 Size
IF1_MEM_TYPE_PARAMETER int 0x0 Interface 1 Mem type
PERIPH_ID_0 int 0x52 Periph_ID_0 value
REMAP int -0x1 Remap the device
revision string "r1p2" Revision
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