3.4 Core components

This section describes the Core components.

These are Code Translation (CT) components. They translate instructions on the fly and cache the translations to enable fast execution of code, but sacrificing timing accuracy. They also use efficient PV bus models to enable fast access to memory and devices.

The CT components implement most of the processor features but differ in certain ways:

  • They do not model cycle timing. In aggregate, all instructions execute in one processor master clock cycle, except for Wait For Interrupt.
  • Write buffers are not modeled on all processors.
  • Most aspects of TLB behavior are implemented in the models. In Arm®v7 models and later, the TLB memory attribute settings are used when stateful cache is enabled.
  • No device-accurate MicroTLB is implemented.
  • Device-accurate modeling of multiple TLBs is off by default.
  • A single memory access port is implemented. The port combines accesses for instruction, data, DMA, and peripherals. Configuration of the peripheral port memory map register is ignored.
  • All memory accesses are atomic and are performed in Programmer’s View (PV) order. Unaligned accesses are always performed as byte transfers.
  • Some instruction sequences are executed atomically so that system time does not advance during their execution. This difference in behavior can affect sequential accesses of device registers where devices are expecting time to move on between each access.
  • Interrupts are not taken at every instruction boundary.
  • Integration and test registers are not implemented.
  • Models do not support running Software Test Libraries (STLs).
  • Not all CP14 debug registers are implemented on all processors.
  • Breakpoint types that the models support directly are:

    • Single address unconditional instruction breakpoints.
    • Single address unconditional data breakpoints.
    • Unconditional instruction address range breakpoints.
  • Pseudoregisters in the debugger support processor exception breakpoints. Setting an exception register to a nonzero value stops execution on entry to the associated exception vector.
  • Cluster models do not simulate all cores at the same time. They execute a number of instructions on each core in turn. There can be a bias in the order in which cores run after a restart (for example, core 0 always runs first), so the simulation might hit breakpoints on the favored core more often.
  • Performance counters are not implemented on all models.
  • Some models implement caches, although all processor models implement cache control registers.
  • Models use a simplified view of the external buses.
This section contains the following subsections:
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