ASYNC_MEMORY_FAULT

Context ID Register write. Fields:

FAULT unsigned int

Fault status in ESR format

PADDR unsigned int

Physical Address (or 0 if unavailable)

VADDR signed int

Virtual Address (or 0 if unavailable)

ATOMIC_END_ACCESS

Bus trace access for atomics. Fields:

ACCESS_FAIL bool

Memory access failed

ADDR unsigned int

The virtual address of the access.

ATTR unsigned int

Transaction Attributes: [11] Non-secure, [10] Privileged, [9:8] shareability domain (0=nsh, 1=ish, 2=osh, 3=system), [7:4] outer memory attributes, [3:0] inner memory attributes ([7]/[3] Allocate (Other Allocate when read), [6]/[2] Allocate (Other Allocate when write), [5]/[1] Modifiable, [4]/[0] Bufferable). All other bits are implementation defined

COMPARE_VALUE unsigned int

Compare value for CAS

LOAD_VALUE unsigned int

Loaded values

NSDESC unsigned int

The security state of the access.

OPERAND_VALUE unsigned int

Operation's operand

OPERATION enum

Operation type

PADDR unsigned int

The physical address of the access.

PRIV bool

Is this a privileged access?

ATOMIC_START_ACCESS

Bus trace access for atomics. Fields:

ADDR unsigned int

The virtual address of the access.

ATTR unsigned int

Transaction Attributes: [11] Non-secure, [10] Privileged, [9:8] shareability domain (0=nsh, 1=ish, 2=osh, 3=system), [7:4] outer memory attributes, [3:0] inner memory attributes ([7]/[3] Allocate (Other Allocate when read), [6]/[2] Allocate (Other Allocate when write), [5]/[1] Modifiable, [4]/[0] Bufferable). All other bits are implementation defined

COMPARE_VALUE unsigned int

Compare value for CAS

NSDESC unsigned int

The security state of the access.

OPERAND_VALUE unsigned int

Operation's operand

OPERATION enum

Operation type

PADDR unsigned int

The physical address of the access.

PRIV bool

Is this a privileged access?

ArchMsg.Warning.TarmacReconstructor

Unexpected event happened during Tarmac reconstruction. Fields:

REASON string

Reason

ArchMsg.Warning.cache_contents_unknown

A cache has been activated without being invalidated and may contain UNKNOWN content. Fields:

REGIME unsigned int

Current translation regime

SIDE unsigned int

0 d-side cache or unified cache, 1 i-side

ArchMsg.Warning.recursive_branch

An instruction is performing a branch that targets the same instruction. If this was intended then a WFI might be more effective. Fields:

PC unsigned int

Address of instruction causing the branch

ArchMsg.Warning.recursive_exception

An instruction has generated an exception that targets the same instruction. Fields:

CPSR unsigned int

Processor state

PC unsigned int

Address of instruction causing the exception

TYPE enum

Type of exception

ArchMsg.Warning.tlb_contents_unknown

Translation has been enabled without invalidating the TLB. Fields:

EL unsigned int

Exception level of translation regime

INVALIDITY unsigned int

Which TLB may be invalid (if TLBs are separate)

NON_SECURE unsigned int

Security state of translation regime

VMID unsigned int

Current VMID, if applicable

BRANCH_MISPREDICT

Simulating branch mispredict. Fields:

PC unsigned int

Origin address (or 0 if unavailable)

BRA_DIR

Direct branches, to immediate address. Fields:

CORE_NUM unsigned int

Core number in a multi processor.

INST_COUNT unsigned int

The core's instruction counter, starting at 1 for the first instruction.

ISET enum

The instructions set of the branch instruction.

IS_COND bool

Indicates if this is a conditional branch.

PC unsigned int

The address of the branch instruction.

TARGET_ISET enum

The instructions set after the branch.

TARGET_PC unsigned int

The address the instruction branches to.

BRA_INDIR

Indirect branches, perhaps to a register. Fields:

CORE_NUM unsigned int

Core number in a multi processor.

INST_COUNT unsigned int

The core's instruction counter, starting at 1 for the first instruction.

ISET enum

The instructions set of the branch instruction.

IS_COND bool

Indicates if this is a conditional branch.

PC unsigned int

The address of the branch instruction.

TARGET_ISET enum

The instructions set after the branch.

TARGET_PC unsigned int

The address the instruction branches to.

CACHE_MAINTENANCE_OP

Cache Maintenance Operation. Fields:

CORE_NUM unsigned int

Core number in a multi processor.

DATA unsigned int

Specified MVA or Set/way

FUNCTION enum

Clean / Invalidate

SCOPE enum

Affected region

SIDE enum

Inst / Data.

CCFAIL

Conditional instruction condition check fail. Fields:

COND enum

The condition of the conditional instruction.

CORE_NUM unsigned int

Core number in a multi processor.

PC unsigned int

The address of the conditional instruction.

CCFAIL_UNC

Unconditional instruction condition check fail. Fields:

COND enum

The condition of the conditional instruction.

CORE_NUM unsigned int

Core number in a multi processor.

PC unsigned int

The address of the conditional instruction.

CCPASS

Conditional instruction condition check pass. Fields:

COND enum

The condition of the conditional instruction.

CORE_NUM unsigned int

Core number in a multi processor.

PC unsigned int

The address of the conditional instruction.

CCPASS_UNC

Unconditional instruction condition check pass. Fields:

COND enum

The condition of the conditional instruction.

CORE_NUM unsigned int

Core number in a multi processor.

PC unsigned int

The address of the conditional instruction.

CODE_CACHE_MAINT

Code cache maintenance. Fields:

TYPE enum

Request type.

VA_END_INCL unsigned int

Inclusive end addres for by VA requests

VA_START unsigned int

Start address for by VA requests

COMPILE_BLOCK_END

Last instruction of basic block translated. Fields:

VADDR unsigned int

Address of next instruction after this basic block

COMPILE_BLOCK_START

First instruction of basic block translated. Fields:

VADDR unsigned int

Address of first instruction in basic block

COMPILE_INST

ARM instruction compiled. Fields:

DISASS string

Disassembly of the instruction.

ISET enum

The instruction set of this instruction.

ITSTATE unsigned int

The ITSTATE current for the instruction.

OPCODE unsigned int

The opcode of the instruction.

PC unsigned int

The address of the instruction.

SIZE unsigned int

The size of the instruction in bytes.

CONTEXTIDR

Context ID Register write. Fields:

CORE_NUM unsigned int

Core number in a multi processor.

NS bool

Secure or nonsecure banked register is accessed.

UNDEF bool

The register accessed is undefined.

VALUE unsigned int

The new value written.

CONTEXT_SYNC

Called for every context synchronization event. Fields:

ARCH_CSE bool

Architectural Context Synchronization Event

SYSREG_SYNC bool

System register synchronization event

CORE_ENDIAN

Core BE8 Big-Endian state changed. Fields:

BE8 bool

Core BE8 Big-Endian state

CORE_INFO

Static processor attributes. Only triggered by a call to DumpState(). Fields:

ARCH_PROFILE enum

The architecture profile of the core.

CLUSTER_ID unsigned int

The cluster ID of this processor.

CORE_NUM unsigned int

The number of this core in an MP processor.

FPU_VERSION enum

The VFP version implemented by the core.

MEM_ARCH enum

The memory architecture of the core.

NUM_CORES unsigned int

The number of cores in this MP processor.

QUANTUM_SIZE unsigned int

The default quantum size of the core.

SECURITY_FEATURES bool

Does the core have security features?

CORE_LOADS

Processor load accesses. Fields:

ACCESS_TYPE enum

The type of instruction performing the access.

ACQREL enum

Is this an acquire/release

ATTR unsigned int

Memory attributes: [11] Non-secure, [10] Privileged, [9:8] shareability domain (0=nsh, 1=ish, 2=osh, 3=system), [7:4] outer memory attributes, [3:0] inner memory attributes ([7]/[3] Allocate (Other Allocate when read), [6]/[2] Allocate (Other Allocate when write), [5]/[1] Modifiable, [4]/[0] Bufferable). All other bits are implementation defined

ATTR2 unsigned int

Second page memory attributes: [11] Non-secure, [10] Privileged, [9:8] shareability domain (0=nsh, 1=ish, 2=osh, 3=system), [7:4] outer memory attributes, [3:0] inner memory attributes ([7]/[3] Allocate (Other Allocate when read), [6]/[2] Allocate (Other Allocate when write), [5]/[1] Modifiable, [4]/[0] Bufferable). All other bits are implementation defined

CURRENT_TIME unsigned int

The core's current time, as simulated time plus local time.

DATA unsigned int

The data read or written.

ELEMENT_SIZE unsigned int

Width of each element.

LOCAL_TIME unsigned int

The core's local time, relative to the current quantum.

LOCK enum

Normal, exclusive or locked access.

NSDESC unsigned int

The physical address non-secure bit.

NSDESC2 unsigned int

The second page physical address non-secure bit.

PADDR unsigned int

The physical (translated) address.

PADDR2 unsigned int

If different from PADDR, the physical address of the second page of the access.

RESPONSE enum

0=Aborted, 1=OK, 2=Exclusive Failed

SIZE unsigned int

Width of the access in bytes. Only required if DATA is not traced.

TRANS bool

Is this a translated access.

VADDR unsigned int

The virtual address of the access.

CORE_REGS

Changes of the core registers R0 to R14. Fields:

CORE_NUM unsigned int

Core number in a multi processor.

ID unsigned int

The register number, 0 to 14.

MODE enum

Bank of the register accessed.

OLD_VALUE unsigned int

The old value overwritten.

PHYS_ID enum

The physical register accessed.

VALUE unsigned int

The new value written to the register.

CORE_STORES

Processor store accesses. Fields:

ACCESS_TYPE enum

The type of instruction performing the access.

ACQREL enum

Is this an acquire/release

ATTR unsigned int

Memory attributes: [11] Non-secure, [10] Privileged, [9:8] shareability domain (0=nsh, 1=ish, 2=osh, 3=system), [7:4] outer memory attributes, [3:0] inner memory attributes ([7]/[3] Allocate (Other Allocate when read), [6]/[2] Allocate (Other Allocate when write), [5]/[1] Modifiable, [4]/[0] Bufferable). All other bits are implementation defined

ATTR2 unsigned int

Second page memory attributes: [11] Non-secure, [10] Privileged, [9:8] shareability domain (0=nsh, 1=ish, 2=osh, 3=system), [7:4] outer memory attributes, [3:0] inner memory attributes ([7]/[3] Allocate (Other Allocate when read), [6]/[2] Allocate (Other Allocate when write), [5]/[1] Modifiable, [4]/[0] Bufferable). All other bits are implementation defined

CURRENT_TIME unsigned int

The core's current time, as simulated time plus local time.

DATA unsigned int

The data read or written.

ELEMENT_SIZE unsigned int

Width of each element.

LOCAL_TIME unsigned int

The core's local time, relative to the current quantum.

LOCK enum

Normal, exclusive or locked access.

NSDESC unsigned int

The physical address non-secure bit.

NSDESC2 unsigned int

The second page physical address non-secure bit.

PADDR unsigned int

The physical (translated) address.

PADDR2 unsigned int

If different from PADDR, the physical address of the second page of the access.

RESPONSE enum

0=Aborted, 1=OK, 2=Exclusive Failed

SIZE unsigned int

Width of the access in bytes. Only required if DATA is not traced.

TRANS bool

Is this a translated access.

VADDR unsigned int

The virtual address of the access.

CP14_READ

Reads to the System Coprocessor registers. Fields:

CORE_NUM unsigned int

Core number in a multi processor.

CRm unsigned int

CRm

CRn unsigned int

CRn

NS bool

Secure or nonsecure banked register is accessed.

REG_NAME string

Name of the CP14 register accessed.

UNDEF bool

The register accessed is undefined.

VALUE unsigned int

The value read.

opc1 unsigned int

opcode 1

opc2 unsigned int

opcode 2

CP14_WRITE

Writes to the System Coprocessor registers. Fields:

CORE_NUM unsigned int

Core number in a multi processor.

CRm unsigned int

CRm

CRn unsigned int

CRn

NS bool

Secure or nonsecure banked register is accessed.

REG_NAME string

Name of the CP14 register accessed.

UNDEF bool

The register accessed is undefined.

VALUE unsigned int

The new value written.

opc1 unsigned int

opcode 1

opc2 unsigned int

opcode 2

CP15_READ

System Coprocessor register read. Fields:

CORE_NUM unsigned int

Core number in a multi processor.

CRm unsigned int

CRm

CRn unsigned int

CRn

NS bool

Secure or nonsecure banked register is accessed.

REG_NAME string

Name of the CP15 register accessed.

UNDEF bool

The register accessed is undefined.

VALUE unsigned int

The value read.

opc1 unsigned int

opcode 1

opc2 unsigned int

opcode 2

CP15_READ64

System Coprocessor register read. Fields:

CORE_NUM unsigned int

Core number in a multi processor.

CRm unsigned int

CRm

NS bool

Secure or nonsecure banked register is accessed.

REG_NAME string

Name of the CP15 register accessed.

UNDEF bool

The register accessed is undefined.

VALUE unsigned int

The value read.

opc unsigned int

opcode 1

CP15_WRITE

System Control Coprocessor register write. Fields:

CORE_NUM unsigned int

Core number in a multi processor.

CRm unsigned int

CRm

CRn unsigned int

CRn

NS bool

Secure or nonsecure banked register is accessed.

REG_NAME string

Name of the CP15 register accessed.

UNDEF bool

The register accessed is undefined.

UPDATED_VALUE unsigned int

Updated value of the register now it has been written.

VALUE unsigned int

The new value written.

opc1 unsigned int

opcode 1

opc2 unsigned int

opcode 2

CP15_WRITE64

System Coprocessor register write. Fields:

CORE_NUM unsigned int

Core number in a multi processor.

CRm unsigned int

CRm

NS bool

Secure or nonsecure banked register is accessed.

REG_NAME string

Name of the CP15 register accessed.

UNDEF bool

The register accessed is undefined.

UPDATED_VALUE unsigned int

Updated value of the register now it has been written.

VALUE unsigned int

The new value written.

opc unsigned int

opcode 1

CPSR

CPSR change. Fields:

CORE_NUM unsigned int

Core number in a multi processor.

OLD_VALUE unsigned int

The old CPSR value

UNKNOWN unsigned int

Bits within the register that have unknown value.

VALUE unsigned int

The new CPSR value

CRYPTO_SPEC

Every crypto instruction speculatively executed.

DATA_CACHE_SET_ALLOC_TAGS

Set allocation tags from DC GVA instruction. Fields:

ATTR unsigned int

Transaction Attributes: [11] Non-secure, [10] Privileged, [9:8] shareability domain (0=nsh, 1=ish, 2=osh, 3=system), [7:4] outer memory attributes, [3:0] inner memory attributes ([7]/[3] Allocate (Other Allocate when read), [6]/[2] Allocate (Other Allocate when write), [5]/[1] Modifiable, [4]/[0] Bufferable). All other bits are implementation defined

NSDESC unsigned int

The security state of the access.

PADDR unsigned int

The physical address of the access.

RESPONSE enum

0=Aborted, 1=OK

SIZE unsigned int

The size of memory in bytes.

TAG unsigned int

The value of the tag being set.

VADDR unsigned int

Virtual address used for setting allocation tags.

DATA_CACHE_ZERO

Zero and invalidate cache line from DC ZVA instruction. Fields:

ATTR unsigned int

Transaction Attributes: [11] Non-secure, [10] Privileged, [9:8] shareability domain (0=nsh, 1=ish, 2=osh, 3=system), [7:4] outer memory attributes, [3:0] inner memory attributes ([7]/[3] Allocate (Other Allocate when read), [6]/[2] Allocate (Other Allocate when write), [5]/[1] Modifiable, [4]/[0] Bufferable). All other bits are implementation defined

NSDESC unsigned int

The security state of the access.

PADDR unsigned int

The physical address of the access.

RESPONSE enum

0=Aborted, 1=OK

SIZE unsigned int

The size of zero'd memory in bytes.

VADDR unsigned int

Virtual address of the zero'd cache line.

END_COMPILE

Compilation end. Fields:

END_OF_PAGE_COUNT unsigned int

Number of basic blocks exited due to page boundary since START_COMPILE.

FETCHFAIL_COUNT unsigned int

Number of basic blocks exited due to ifetch failure START_COMPILE.

INST_COUNT unsigned int

Number of instructions compiled since START_COMPILE.

NONSEQ_COUNT unsigned int

Number of basic blocks exited due to non-sequential instructions since START_COMPILE.

PAGE_STRADDLE_COUNT unsigned int

Number of basic blocks exited due to unaligned instructions crossing page since START_COMPILE.

EXCEPTION

Exception taken. Fields:

CORE_NUM unsigned int

Core number in a multi processor.

IS_PHYSICAL bool

Physical or Virtual exception

LR unsigned int

The value assigned to the link register.

PC unsigned int

The location where the exception occurred.

PREFERRED_RETURN unsigned int

The preferred return address for the exception.

TARGET_ISET enum

The instruction set of the exception handler code.

TARGET_PC unsigned int

The address the exception branches to.

VECTOR enum

The exception vector.

VECTOR_OFFSET unsigned int

The offset of an exception vector from the base address.

EXCEPTION_END

Every exception completed.

EXCEPTION_RAISE

Every exception raised.

EXCEPTION_RETURN

Branches on leaving exception. Fields:

CORE_NUM unsigned int

Core number in a multi processor.

INST_COUNT unsigned int

The core's instruction counter, starting at 1 for the first instruction.

ISET enum

The instructions set of the branch instruction.

IS_COND bool

Indicates if this is a conditional branch.

PC unsigned int

The address of the branch instruction.

TARGET_ISET enum

The instructions set after the branch.

TARGET_PC unsigned int

The address the instruction branches to.

EXCEPTION_RETURN_PREBRANCH

Exception return event that must occur before PC and processor state have updated.

EXCEPTION_START

Every exception started.

FP_STATE

Floating point state. Fields:

FPSR unsigned int

FPSR register value.

MASK unsigned int

The mask indicating updated cumulative bits.

HLT

HLT instruction occurred. Fields:

IMM16 unsigned int

The 16-bit immediate value encoded in HLT instruction.

INST

Every instruction executed. Fields:

CORE_NUM unsigned int

Core number in a multi processor.

CURRENT_TIME unsigned int

The core's current time, as simulated time plus local time.

DISASS string

Disassembly of instruction.

INST_COUNT unsigned int

The core's instruction counter, starting at 1 for the first instruction.

ISET enum

The current instruction set.

ITSTATE unsigned int

The current ITSTATE.

LOCAL_TIME unsigned int

The core's local time, relative to the current quantum.

MODE enum

The mode the core is in.

NS unsigned int

The core's non-secure bit.

NSDESC unsigned int

The physical address non-secure bit.

NSDESC2 unsigned int

The second page physical address non-secure bit.

OPCODE unsigned int

The opcode of the instruction.

PADDR unsigned int

The physical address of the instruction.

PADDR2 unsigned int

If different from PADDR, the physical address of the second page of the instruction.

PC unsigned int

The address of the instruction.

SIZE unsigned int

The size of the instruction in bytes.

INST_END

Every instruction completed.

INST_START

Every instruction started. Fields:

ISET enum

The current instruction set.

MODE enum

The mode the core is in.

NS enum

The current Secure State.

PC unsigned int

The address of the conditional instruction.

INST_STRADDLE

Instruction straddles boundary. Fields:

ISET enum

The current instruction set.

MODE enum

The mode the core is in.

NS enum

The current Secure State.

PC unsigned int

The address of the conditional instruction.

LOAD_MULTIPLE_REGS_LIST

List of destination registers (not source) of a multiple registers load instruction. Fields:

REG string

Register to add into the list

LOCAL_MONITOR

Local monitor activity. Fields:

PADDR unsigned int

Local Monitor Address

State enum

State of the monitor (Open/Exclusive)

MMU_TRANS

Address translation information. Fields:

ASID unsigned int

Address space identifier.

CORE_NUM unsigned int

Core number in a multi processor.

Hyp bool

Entry matches in Hyp state only

INNERCACHE_RA bool

Is the inner cache allocate on read

INNERCACHE_TRANSIENT bool

Is the inner write-through transient

INNERCACHE_TYPE enum

Inner Caching scheme (NC/MB/WA).

INNERCACHE_WA bool

Is the inner cache allocate on write

MEMTYPE enum

Memory type.

NSDESC enum

Is secure side supposed to access secure or nonsecure memory

OUTERCACHE_RA bool

Is the outer cache allocate on read

OUTERCACHE_TRANSIENT bool

Is the outer write-through transient

OUTERCACHE_TYPE enum

Outer Caching scheme (NC/MB/WA).

OUTERCACHE_WA bool

Is the outer cache allocate on write

PADDR unsigned int

Physical address of the access.

PAGESIZE unsigned int

Page size as log2(size).

SH enum

Shareability

SIDE enum

Inst / Data.

STAGE1_PERM unsigned int

Stage 1 permissions, [5:3] Privileged access (XWR) [2:0] User access (XWR)

STAGE2_PERM unsigned int

Stage 2 permission mask [5:3] Privileged access (XWR) [2:0] User access (XWR)

VADDR unsigned int

Virtual address of the access.

VMID unsigned int

Virtual machine identifier.

nG enum

Flag indicating whether ASID will be matched

MMU_TTB_READ

This event is triggered by reads caused by a translation table walk. Fields:

ABORTED bool

Was the walk successful.

DATA unsigned int

The data read.

IPA unsigned int

For stage 1, the IPA of the read.

LEVEL unsigned int

Translation table level

LPAE bool

Is this for an LPAE translation

NSmem bool

Non secure memory access

NSreq bool

Non secure request

PADDR unsigned int

The physical address of the read.

SIDE enum

Inst / Data.

STAGE unsigned int

Translation stage

MMU_TTB_WRITE

This event is triggered by writes caused by a translation table walk. Fields:

ABORTED bool

Was the walk successful.

DATA unsigned int

The data written.

IPA unsigned int

For stage 1, the IPA of the write.

LEVEL unsigned int

Translation table level

LPAE bool

Is this for an LPAE translation

NSmem bool

Non secure memory access

NSreq bool

Non secure request

PADDR unsigned int

The physical address of the write.

SIDE enum

Inst / Data.

STAGE unsigned int

Translation stage

MODE_CHANGE

Mode change. Fields:

CORE_NUM unsigned int

Core number in a multi processor.

MODE enum

The new mode.

NON_SECURE enum

The new security state

OLD_MODE enum

The old mode.

PERIODIC

Called for every quantum. Fields:

CORE_NUM unsigned int

Core number in a multi processor.

INST_COUNT unsigned int

The instruction count of this CPU.

PC unsigned int

The address of the next instruction to be executed on this CPU.

PMU_COUNTER_OVERFLOW

PMU counter overflow. Fields:

EVENT_ID unsigned int

Event Identifier

INDEX unsigned int

Counter index (as selected by PMSELR).

INTERRUPT bool

Is interrupt enabled on overflow for this counter

PRELOAD_DATA

Data preload from PLD instruction. Fields:

VADDR unsigned int

Virtual address of the data that should be preloaded.

PRELOAD_INST

Instruction preload from PLI instruction. Fields:

VADDR unsigned int

Virtual address of the instruction that should be preloaded.

PRE_CORE_LOAD

Trace just before a core load. Fields:

CURRENT_TIME unsigned int

The core's current time, as simulated time plus local time.

LOCAL_TIME unsigned int

The core's local time, relative to the current quantum.

PRE_CORE_STORE

Trace just before a core store. Fields:

CURRENT_TIME unsigned int

The core's current time, as simulated time plus local time.

LOCAL_TIME unsigned int

The core's local time, relative to the current quantum.

PRE_TTB_READ

This event is triggered before reads caused by a translation table walk. Fields:

ADDR unsigned int

The physical address of the read.

PSTATE_PACTIVE_OPMODE_TRANSITION

Trace pactive and Opmode mode transitions on PChannel. Fields:

DEVPACTIVE unsigned int

Integer representation of DEVPACTIVE[] signals

NEW_STATE enum

Operating mode after the transition

OLD_STATE enum

Operating mode before the transition

PSTATE_PACTIVE_OPMODE_TRANSITION_DENIED

Trace the denied pactive and Opmode mode transitions on PChannel. Fields:

DEVPACTIVE unsigned int

Integer representation of DEVPACTIVE[] signals

NEW_STATE enum

Operating mode after the transition

OLD_STATE enum

Operating mode before the transition

REASON string

Reason for the transition being denied

PSTATE_PACTIVE_POWER_TRANSITION

Trace pactive and power mode transitions on PChannel. Fields:

DEVPACTIVE unsigned int

Integer representation of DEVPACTIVE[] signals

NEW_STATE enum

Power mode after the transition

OLD_STATE enum

Power mode before the transition

PSTATE_PACTIVE_POWER_TRANSITION_DENIED

Trace the denied pactive and power mode transitions on PChannel. Fields:

DEVPACTIVE unsigned int

Integer representation of DEVPACTIVE[] signals

NEW_STATE enum

Power mode after the transition

OLD_STATE enum

Power mode before the transition

REASON string

Reason for the transition being denied

PSTATE_PACTIVE_THREAD_OPMODE_TRANSITION

Trace pactive and Opmode mode transitions for threads on PChannel. Fields:

DEVPACTIVE unsigned int

Integer representation of DEVPACTIVE[] signals

NEW_STATE enum

Operating mode after the transition

OLD_STATE enum

Operating mode before the transition

RUN_STATE

Run state transition. Fields:

INST_COUNT unsigned int

Ticks count at point of transition.

NEW enum

New run state.

OLD enum

Old run state.

SEMIHOSTING_CALL

Call of a semihost function occurred. Fields:

PC unsigned int

The program counter after the semihosting call.

SEMIHOSTING_PRECALL

About to call semihost. Fields:

EL2 bool

Use EL2 translation regime.

NS bool

Is Non-Secure.

REG_WIDTH unsigned int

The current register width in bytes.

SIGNAL

External signal state change. Fields:

SIGNAL enum

Signal that changed

STATE bool

Signal asserted state

SPSR

SPSR change. Fields:

CORE_NUM unsigned int

Core number in a multi processor.

MODE enum

Which of the banked SPSR registers is written.

OLD_VALUE unsigned int

The old SPSR value

VALUE unsigned int

The new SPSR value

START_COMPILE

Compilation started. Fields:

VADDR unsigned int

Instruction where compilation begins.

STORE_MULTIPLE_REGS_ADDRESS_RANGE

Address range for stores with multiple registers. Fields:

ADDR_END unsigned int

Final address.

ADDR_START unsigned int

Starting address.

SUBOPTIMAL_LDST_RETIRED

suboptimal load/store. Fields:

ACCESS_SIZE unsigned int

Log2 of the access width in bytes used for alignment checking (1: half-word, 2: word ...)

OPTIMAL_ALIGN_SELECTOR unsigned int

Selector to decide the optimal alignment size (1: access width, 2: 4-bytes, 3: 8-bytes, ..., 12: 4-kbytes)

VADDR unsigned int

The virtual address of the access

SYNC

Called for every synchronization. Fields:

CORE_NUM unsigned int

Core number in a multi processor.

INST_COUNT unsigned int

The instruction count of this CPU.

LOCAL_QUANTUM unsigned int

The local quantum of this CPU.

LOCAL_TIME unsigned int

The local time of this CPU.

SYSCALL

System call instruction executed. Fields:

IMM unsigned int

Immediate value of the system call instruction.

TYPE enum

System call type.

VADDR unsigned int

Instruction that caused the system call.

SYSREG_READ64

System Coprocessor register read. Fields:

CORE_NUM unsigned int

Core number in a multi processor.

REGNUM enum

Internal register number

UNDEF bool

The register accessed is undefined.

VALUE unsigned int

The value read.

SYSREG_UPDATE32

Triggers when the system updates a register. Fields:

REG enum

Register number.

UNKNOWN unsigned int

Bits of the register which became unknown.

VALUE unsigned int

Value written to the register.

SYSREG_UPDATE64

Triggers when the system updates a register. Fields:

REG enum

Register number.

UNKNOWN unsigned int

Bits of the register which became unknown.

VALUE unsigned int

Value written to the register.

SYSREG_WRITE64

System Coprocessor register write. Fields:

CORE_NUM unsigned int

Core number in a multi processor.

REGNUM enum

Internal register number

UNDEF bool

The register accessed is undefined.

UPDATED_VALUE unsigned int

Updated value of the register now it has been written.

VALUE unsigned int

The new value written.

UNALIGNED_LDST_RETIRED

Processor unaligned load/store. Fields:

ACCESS_SIZE unsigned int

Log2 of the access width in bytes used for alignment checking (1=>half-word, 2->word ...)

NUMBER_OF_BEATS unsigned int

Number of accesses (beats) in this burst (Total size in bytes is ACCESS_SIZE * NUMBER_OF_BEATS)

VADDR unsigned int

The virtual address of the access

VFP_D_REGS

VFP/NEON D 64 bit register write. Fields:

ALIASING enum

Type of register aliasing used

CORE_NUM unsigned int

Core number in a multi processor.

ID unsigned int

The register number.

MASK unsigned int

Each bit indicates a write to the corresponding bit in the register. For example, 0x1 would indicate a write to VALUE[0]

OLD_VALUE unsigned int

The old value overwritten.

VALUE unsigned int

The new value written to the register.

VFP_Q_REGS

VFP/NEON Q 128 bit register write. Fields:

ALIASING enum

Type of register aliasing used

CORE_NUM unsigned int

Core number in a multi processor.

ID unsigned int

The register number.

MASK unsigned int

Each bit indicates a write to the corresponding byte in the register. For example, 0x1 would indicate a write to VALUE[7:0]

OLD_VALUE unsigned int

The old value overwritten.

VALUE unsigned int

The new value written to the register.

VFP_SYS_REGS

Writes to the VFP/NEON units system registers. Fields:

CORE_NUM unsigned int

Core number in a multi processor.

ID enum

Which VFP system register is written.

OLD_VALUE unsigned int

The register's old value overwritten.

VALUE unsigned int

The new value written to the VFP system register.

VFP_S_REGS

VFP/NEON S 32 bit register write. Fields:

ALIASING enum

Type of register aliasing used.

CORE_NUM unsigned int

Core number in a multi processor.

ID unsigned int

The register number.

MASK unsigned int

Each bit indicates a write to the corresponding bit in the register. For example, 0x1 would indicate a write to VALUE[0]

OLD_VALUE unsigned int

The old value overwritten.

VALUE unsigned int

The new value written to the register.

WAYPOINT

Signals end of basic block execution. Fields:

CORE_NUM unsigned int

Core number in a multi processor.

ISET enum

Origin instructions set

IS_COND bool

Indicates if this is a conditional waypoint.

PC unsigned int

Origin address (or 0 if unavailable)

TAKEN bool

Indicates if this waypoint was taken.

TARGET unsigned int

Destination address

TARGET_ISET enum

Destination instructions set

WFE_END

WFE ended. Fields:

INST_COUNT unsigned int

Ticks count when leaving WFE.

WFE_EVENT_REGISTER

WFE event register status: set/clear, reason. Fields:

INST_COUNT unsigned int

Ticks count.

REASON enum

Reason for set/clear. Only REASON==0 (Cleared by WFE) clears the bit, all other reasons set it.

WFE_IGNORED

WFE ignored. Fields:

EVENT bool

This WFE was ignored because the event register was set.

INST_COUNT unsigned int

Ticks count when ignoring WFE.

TRAPPED bool

This WFE was trapped.

WFE_START

WFE entered. Fields:

INST_COUNT unsigned int

Ticks count when entering WFE.

WFI_END

WFI ended. Fields:

INST_COUNT unsigned int

Ticks count when leaving WFI.

WFI_IGNORED

WFI ignored. Fields:

DISABLED bool

This WFI was ignored because WFI is disabled.

INST_COUNT unsigned int

Ticks count when ignoring WFI.

REASON enum

specifies reason why WFI trace was ignored

TRAPPED bool

This WFI was trapped.

WFI_START

WFI entered. Fields:

INST_COUNT unsigned int

Ticks count when entering WFI.

WFI_WAKEUP

WFI wakeup. Fields:

INST_COUNT unsigned int

Ticks count when WFI wakeup occurred.

REASON enum

Reason for wakeup.