3.10.66 v7_VGIC

System VGIC architecture version v7. This model is written in C++.

v7_VGIC contains the following CADI targets:

  • v7_VGIC

v7_VGIC contains the following MTI components:

Table 3-403 Ports

Name Protocol Type Description
cfgsdisable Signal Slave Disable write access to some GIC registers.
configuration v7_VGIC_Configuration_Protocol Slave Configure the mapping of the core number (from MasterID) to the core interface number.
fiq_in[8] Signal Slave FIQ inputs.
fiq_out[8] Signal Master FIQ outputs.
irq_in[8] Signal Slave IRQ intputs.
irq_out[8] Signal Master IRQ outputs.
ppi_core0[16] Signal Slave Private peripheral interrupts (ID16-ID31) for cpu 0.
ppi_core1[16] Signal Slave Private peripheral interrupts (ID16-ID31) for cpu 1.
ppi_core2[16] Signal Slave Private peripheral interrupts (ID16-ID31) for cpu 2.
ppi_core3[16] Signal Slave Private peripheral interrupts (ID16-ID31) for cpu 3.
ppi_core4[16] Signal Slave Private peripheral interrupts (ID16-ID31) for cpu 4.
ppi_core5[16] Signal Slave Private peripheral interrupts (ID16-ID31) for cpu 5.
ppi_core6[16] Signal Slave Private peripheral interrupts (ID16-ID31) for cpu 6.
ppi_core7[16] Signal Slave Private peripheral interrupts (ID16-ID31) for cpu 7.
pvbus_s PVBus Slave Bus port for accessing distributor registers.
reporting_interface VGICReportingProtocol Slave Logging interface.
reset_signal Signal Slave Reset signal input.
spi[988] Signal Slave SPI inputs.
vfiq_out[8] Signal Master Virtual FIQ outputs.
virq_out[8] Signal Master Virtual IRQ outputs.
wakeup_fiq[8] Signal Master Wakeup signal for FIQ.
wakeup_irq[8] Signal Master Wakeup signal for IRQ.

Table 3-404 Parameters for v7_VGIC

Name Type Default value Description
enable_log_errors bool 0x0 Enable logging of errors
enable_log_fatal bool 0x0 Enable logging of fatal errors
enable_log_warnings bool 0x0 Enable logging of warnings
enabled bool 0x1 Enable the component. If it is disabled then all register writes will have no effect.
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