10.7.1 Configuring instruction prefetching

Configure instruction cache prefetching for AEMv8-A processor models by using the following cluster-level parameters:

icache-prefetch_enabled
true to enable simulation of instruction cache prefetching, false otherwise. Defaults to false.
The execution of a branch instruction causes the model to prefetch instructions from the memory region starting at the branch target address into a number of sequential cache lines. If true, the following extra parameters are available:
icache-prefetch_level
Specifies the zero-indexed cache level into which instructions are prefetched. Defaults to 0, which means L1.
icache-nprefetch
Specifies the number of additional, sequential instruction cache lines to prefetch. Defaults to 1.

Note:

These parameters only have an effect when cache state modeling is enabled, which is controlled by the model parameter icache-state_modelled.

Example

The following command-line enables instruction cache prefetching and displays WAYPOINT trace events in the console:

Note:

A WAYPOINT is a point at which instruction execution by the processor might change the program flow.
./FVP_Base_AEMv8A.exe -a $PVLIB_HOME/images/brot.axf \ 
-C cache_state_modelled=1 \ 
-C cluster0.icache-prefetch_enabled=1 \ 
-C bp.secure_memory =false \ 
--plugin $PVLIB_HOME/plugins/Linux64_GCC-4.8/GenericTrace.so \
-C TRACE.GenericTrace.trace-sources=WAYPOINT
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