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This glossary defines some of the Arm®-specific technical terms and acronyms that are used in the Fast Models documentation.
A set of classes and interfaces that model AMBA® buses. They are implemented as an extension to the TLM v2.0 standard.
See AMBA-PV extensions.
A model of the Arm architecture that aims to expose software bugs by modeling the extremes of behavior that the Arm architecture allows.
A Fast Models feature that SimGen uses to automatically convert between LISA+ protocols and their SystemC equivalents. It helps to automate the generation of SystemC wrappers for LISA+ subsystem models.
See 7.4 Auto-bridging.
An example platform that is provided as part of Fast Models. It is capable of booting Linux and Android. Variations of this platform are available for various core types, and with additional system IP. They are often used together with Linux images that Linaro provides.
See Base Platform.
A C++ interface that is used by debuggers to control a model. CADI enables convenient and accurate debugging of Fast Models and Cycle Models.
A technique that processor models use to enable fast execution of code. CT models translate code dynamically and cache translated code sequences to achieve fast simulation speeds.
Cycle-accurate software models of Arm IP, for example processors or peripherals. They are cycle-accurate and functionally accurate, so are usable for benchmarking. Cycle Models is a separate product from Fast Models, but they can be used alongside each other, in particular by using the Cycle Models Swap-and-Play feature.
A TLM 2.0 interface that provides direct access to memory. It accelerates memory transactions, which improves model performance.
A SystemC module that is generated by using the SystemC Export feature to export a Fast Models subsystem.
High performance software models of components of Arm SoCs, for example processors or peripherals. Components might have subcomponents to form a hierarchy, and might be connected together to form a platform model. Fast Models are functionally accurate, but not cycle-accurate.
A pre-built platform model that enables applications and operating systems to be written and debugged without the need for real hardware. FVPs are also referred to as Fixed Virtual Prototypes. They were formerly known as RTSMs.
See About FVPs.
See Foundation Platform.
A freely available, easy-to-use FVP for application developers that models the Armv8‑A architecture. It can be downloaded from the Arm® Self-Service Portal, registration and login are required. Foundation Platform was formerly known as Foundation Model.
Used in register descriptions in the Fast Models Reference Manual to indicate behavior that the architecture does not define. Short for Implementation Defined.
An executable model binary that can run standalone, without the need for Model Shell or Model Debugger. ISIMs are generated by simgen by statically linking a model with the SystemC framework. ISIMs simplify model debugging and profiling.
LISA is a language that describes instruction set architectures. LISA+ is an extended form of LISA that supports peripheral modeling. LISA+ is used for creating and connecting model components. The Fast Models documentation does not always distinguish between the two terms, and sometimes uses LISA to mean both.
Arm Versatile™ Express V2M-MPS2 and V2M-MPS2+ are motherboards that enable software prototyping and development for Cortex®‑M processors. The MPS2 FVP models a subset of the functionality of this hardware.
See MPS2 - about.
A Fast Models debugger that enables you to execute, connect to, and debug any CADI-compliant model. You can run Model Debugger using a GUI or from the command line.
See About Model Debugger.
A command-line utility for configuring and running CADI-compliant models. Arm deprecates Model Shell from Fast Models version 11.2. Use ISIM executables instead.
See About Model Shell.
A trace interface that is used by Fast Models to expose real-time information from the model.
A model of a development platform, for example an FVP.
A high performance, functionally accurate model of a hardware platform. It can be used for booting an operating system and executing software, but not to provide hardware-accurate timing information.
See Timing Annotation.
An abstract, programmers view model of the communication between components. Bus masters generate transactions over the PVBus and bus slaves fulfill them.
See PVBus components.
A set of instructions that the processor issues at the same point in simulation time. The processor then waits until other components in the system have executed the instructions for the same time slice, before executing the next quantum.
An obsolete term for Fixed Virtual Platform (FVP).
An alternative term for System Generator.
An interface that provides a subset of CADI functions to synchronously read and write registers and memory. You can only call SCADI functions from the model thread itself, rather than from a debugger thread. SCADI is typically used from within MTI or by peripheral components to access the model state and to perform run control.
See About SCADI.
Each processor model has a syncLevel with four possible values. It determines when a synchronous watchpoint or an external peripheral breakpoint can stop the model, and the accuracy of the model state when it is stopped.
An application that enables you to manage and build model systems using components. It has a block diagram editor for adding and connecting model components and setting parameters.
Similar to an FVP, except that the interconnections between components are defined in SystemC rather than in LISA.
A utility that uses a project file containing configuration information to generate a platform model. You can run System Generator from the command line, by invoking the simgen executable, or from the System Canvas GUI.
An alternative term for Platform Model.
A textual trace of the program that is executing on the model. Fast Models provides a Tarmac plugin to produce this trace format.
See Tarmac Trace.
A set of Fast Models features that allow timing configuration for various operations, for instance instruction execution and branch prediction. This allows the model to be used for basic benchmarking.
A family of Arm hardware development boards. The term is abbreviated to VE when used in model names. For example, FVP_VE_Cortex-A5x1 is an FVP model of the Versatile Express hardware platform, containing a single Cortex‑A5 processor.