9.2 Enabling and disabling timing annotation

The environment variable FASTSIM_DISABLE_TA can be used to enable or disable timing annotation latency.

For example, if you set FASTSIM_DISABLE_TA to 1 and you load a timing annotation plug-in, or use a timing annotation feature, for example CPI or cache latency modeling, none of the timing annotation latencies that are computed are injected into the model. In other words, the simulated CPU time is the same for all instructions, that is 1 cycle per instruction.


You can view timing statistics by using the --stat parameter.

Disabling timing annotation does not prevent timing annotation plug-ins from working. For example, the PipelineModel plug-in continues to process instructions and generate statistics, and the BranchPrediction plug-in continues to predict branches and generate statistics files. However, any pipeline stall latencies or branch misprediction penalties that they calculate are ignored by the Fast Models simulation engine.


By default, timing annotation is disabled for SystemC ISIMs. To enable it, set FASTSIM_DISABLE_TA to 0.
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