9.7 Configuring cache and TLB latency

You can configure latency for different cache operations for Cortex®‑A processor models by setting model parameters.

The following parameters are available:

Note:

  • These parameters can only used when cache state modeling is enabled. This is controlled using parameters, for example dcache-state_modelled and icache-state_modelled.
  • All of these latency values are measured in clock ticks.
  • For reads and writes, latency can be specified per access, for example dcache-read_access_latency, or per byte, for example dcache-read_latency. If both parameters are set, the per-access value takes precedence over the per-byte value.
Non-ConfidentialPDF file icon PDF version100965_1180_00_en
Copyright © 2014–2019 Arm Limited or its affiliates. All rights reserved.