Fast Models Fixed Virtual Platforms (FVP) Reference Guide : 3.8.2 Base

This section describes the Base_PowerController component.

The Base_PowerController provides a basic register interface for software to control the power-up and power-down of cores in the cluster.

Identify cores in the system to the Base_PowerController by writing 24 bits in MPIDR format, providing the following levels of affinity:

Examples of affinity usage are not_applicable/cluster/processor and cluster/processor/thread.

This section describes the parameters.

Table 3-11 Base_PowerController parameters

Parameter	Allowed values	Default value	Description
`startup`	-	'0.0.0.*'	A comma-separated list of cores to power up at startup or system reset. Specify core affinities with a dotted-quad ('0.0.0.0' refers to cluster0.cpu0 and '0.0.1.1' refers to cluster1.cpu1). Use wildcards to indicate all cores at an affinity level ('0.0.0.*' indicates all cores in cluster 0 and is equivalent to '0.0.0.0,0.0.0.1,0.0.0.2,…,0.0.0.255').

This section describes the registers.

This section describes the power control registers in order of offset from the base memory address.

Table 3-12 Base_PowerController register summary

Offset	Name	Type	Reset	Width	Description
`0x00`	PPOFFR	RW	`0x---`	32	Power Control Processor Off Register
`0x04`	PPONR	RW	`0x---`	32	Power Control Processor On Register
`0x08`	PCOFFR	RW	`0x---`	32	Power Control Cluster Off Register
`0x0C`	PWKUPR	RW	`0x---`	32	Power Control Wakeup Register
`0x10`	PSYSR	RW	`0x---`	32	Power Control SYS Status Register

The Power Control Processor Off Register (PPOFFR) characteristics are: purpose, usage constraints, configurations, and attributes.

Purpose: Processor SUSPEND command when PWKUPR and the GIC are programmed appropriately to provide wakeup events from IRQ and FIQ events to that processor.
Usage constraints: Processor must make power-off requests only for itself.
Configurations: Available in all configurations.
Attributes: See the register summary table.

Figure 3-1 Power Control Processor Off Register bit assignments

Table 3-13 Power Control Processor Off Register bit assignments

Bits	Name	Function
[31:24]	-	Reserved.
[23:0]	ID	MPIDR format affinity value of the processor to be switched off. Programming error if MPIDR != self.

The Power Control Processor On Register (PPONR) characteristics are: purpose, usage constraints, configurations, and attributes.

Purpose: Brings up a processor from low-power mode.
Usage constraints: Processor must make power-on requests only for other powered-off processors in the system.
Configurations: Available in all configurations.
Attributes: See the register summary table.

Figure 3-2 Power Control Processor On Register bit assignments

Table 3-14 Power Control Processor On Register bit assignments

Bits	Name	Function
[31:24]	-	Reserved.
[23:0]	ID	MPIDR format affinity value of the processor to be switched on. Programming error if MPIDR == self.

The Power Control Cluster Off Register (PCOFFR) characteristics are: purpose, usage constraints, configurations, and attributes.

Figure 3-3 Power Control Cluster Off Register bit assignments

Table 3-15 Power Control Cluster Off Register bit assignments

Bits	Name	Function
[31:24]	-	Reserved.
[23:0]	ID	MPIDR format affinity value of powered-on processor in the cluster to be switched off. Programming error if MPIDR != self.

The Power Control Wakeup Register (PWKUPR) characteristics are: purpose, usage constraints, configurations, and attributes.

Purpose: Configures whether wakeup requests from the GIC are enabled for this cluster.
Usage constraints: There are no usage constraints.
Configurations: Available in all configurations.
Attributes: See the register summary table.

Figure 3-4 Power Control Wakeup Register bit assignments

Table 3-16 Power Control Wakeup Register bit assignments

Bits	Name	Function
[31]	WEN	If set, enables wakeup interrupts (return from SUSPEND) for this cluster.
[30:24]	-	Reserved.
[23:0]	ID	MPIDR format affinity value of processor whose Wakeup Enable bit is to be configured.

The Power Control SYS Status Register (PSYSR) characteristics are: purpose, usage constraints, configurations, and attributes.

Purpose: Provides information on the powered status of a given core. Software writes bits [23:0] for the required core and reads the value along with the associated status in bits [31:24].
Usage constraints: There are no usage constraints.
Configurations: Available in all configurations.
Attributes: See the register summary table.

Figure 3-5 Power Control SYS Status Register bit assignments

Table 3-17 Power Control SYS Status Register bit assignments

Bits	Name	Function
[31]	L2	Read-only. A value of 1 indicates that affinity level 2 is active/on. If affinity level 2 is not implemented this bit is RAZ.
[30]	L1	Read-only. A value of 1 indicates that affinity level 1 is active/on. If affinity level 1 is not implemented this bit is RAZ.
[29]	L0	Read-only. A value of 1 indicates that affinity level 0 is active/on.
[28]	WEN	Read-only. A value of 1 indicates wakeup interrupts, return from SUSPEND, enabled for this processor. This is an alias of PWKUPR.WEN for this core.
[27]	PC	Read-only. A value of 1 indicates pending cluster off, the cluster enters low-power mode the next time it raises signal STANDBYWFIL2.
[26]	PP	Read-only. A value of 1 indicates pending processor off, the processor enters low-power mode the next time it raises signal STANDBYWFI.
[25:24]	WK	Read-only. Indicates the reason for LEVEL0 power on: `0b00` Cold power-on. `0b01` System reset pin. `0b10` Wake by PPONR. `0b11` Wake by GIC WakeRequest signal.
[23:0]	ID	MPIDR format affinity value.

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