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The Base Platform RevC includes the following changes from the previous revision.
It includes a PCIe config region and two PCIe memory regions. See the memory map for details.
It includes a CoreLink™ CCI-550 Cache Coherent Interconnect.
It includes an SMMUv3 AEM. This is an architectural model that implements the SMMUv3.0 and SMMUv3.1 architectures. These architectures are for I/O virtualization of devices. The SMMU is placed so that accesses to memory by PCI devices acting as bus masters are affected by it.
The SMMU has the following features:
Memory that is mapped to the range
Interrupts with IRQ IDs in the range 103-111.
The event output pin of the SMMU is passed to the clusters.
The downstream ports of the SMMU attach to the coherent bus infrastructure and so are coherent with the core clusters. All cores and the SMMU are in the same shareability domain. There is no distinction between the inner and outer shareability domains.
The parameters of the SMMU determine its capabilities and have default values which can be overwritten if necessary.
The SMMU is configured to only accept 16-bit StreamIDs and there is a 1:1 correspondence between RequestorID and StreamID.
By default, the SMMU uses DeviceID
0x10000 to identify itself to the GIC
gic_distributor.ITS-device-bits is set to 17 by default to
support the 17-bit DeviceIDs.
The SMMU has the following limitations:
SMMU_PMCG_CEID0fields. The PMU is intended for demonstration purposes only and for driver development.
Two PCIe virtio devices are above the SMMU. By default they are configured to be device 0 and 2 on bus 0.
The PCIe devices use a DeviceID that is the same as their RequestorID (BDF).
Legacy PCI interrupts:
Each PCI device is hardwired to use INTA, with a value of 1 in the
interrupt_pin register. This is required by
the PCI specification for single-function devices.
The interrupts in the PCI host bridge are mapped according to section 2.2.6 of the PCI Local Bus Specification Revision 3.0, using the following formula, where the values for DeviceInterrupt are INTA = 0, INTB = 1, INTC = 2, INTD = 3:
BridgeInterrupt = (Device + DeviceInterrupt) % 4
This formula produces the following mappings:
The model optionally implements MSI-X, depending on whether a parameter is set. If this parameter is set, an MSI-X capability is advertised as a PCI capability.
The MSIs produced by the models, when directed to the GIC, have their payload rewritten to carry the DeviceID of the originating device to the GIC.
The processor models implement architecture version v8.0, which does not
support the Statistical Profiling Extension (SPE). To include SPE, add parameter
cluster0.has_arm_v8-3=1, or similar, to the