3.4 Base - memory

This section describes the memory of the Base Platform.

3.4.1 Base - secure memory

Enable security checking on memory transactions by the TZC-400 by using the bp.secure_memory parameter.

Table 3-3 Secure and Non-secure access permissions

Security bp.secure_memory=false bp.secure_memory=true
S Secure and Non-secure access permitted. Secure access is permitted, Non-secure access aborts.
S/NS Secure and Non-secure access permitted. Secure and Non-secure access permitted.
P Secure and Non-secure access permitted. Access conditions are programmable by the TZC-400.

Note:

The default state of the TZC-400 is to abort all accesses, even from Secure state.

Table 3-4 NSAIDs and filters that masters present to the TZC-400

Component NSAIDa Filter
Cluster 0 9 0
Cluster 1 9 0
VirtIO 8 0
HDLCD0 2 2
CLCD 1 2

3.4.2 Base - memory map

The basis of this map is the Versatile™ Express RS2 memory map with extensions.

Table 3-5 Base Platform memory map

Peripheral Start address Size End address Security
Trusted Boot ROM, secure flash, IntelStrataFlashJ3 0x00_0000_0000 64MB 0x00_03FF_FFFF S
Trusted SRAM 0x00_0400_0000 256KB 0x00_0403_FFFF S
Trusted DRAM 0x00_0600_0000 32MB 0x00_07FF_FFFF S
NOR flash, flash0, IntelStrataFlashJ3 0x00_0800_0000 64MB 0x00_0BFF_FFFF S/NS
NOR flash, flash1, IntelStrataFlashJ3 0x00_0C00_0000 64MB 0x00_0FFF_FFFF S/NS
PSRAMb 0x00_1400_0000 64MB 0x00_17FF_FFFF S/NS
VRAM 0x00_1800_0000 32MB 0x00_19FF_FFFF S/NS
Ethernet, SMSC 91C111 0x00_1A00_0000 16MB 0x00_1AFF_FFFF S/NS
USB, unimplemented 0x00_1B00_0000 16MB 0x00_1BFF_FFFF S/NS
VE System Registers 0x00_1C01_0000 64KB 0x00_1C01_FFFF S/NS
System Controller, SP810 0x00_1C02_0000 64KB 0x00_1C02_FFFF S/NS
AACI, PL041 0x00_1C04_0000 64KB 0x00_1C04_FFFF S/NS
MCI, PL180 0x00_1C05_0000 64KB 0x00_1C05_FFFF S/NS
KMI - Keyboard, PL050 0x00_1C06_0000 64KB 0x00_1C06_FFFF S/NS
KMI - Mouse, PL050 0x00_1C07_0000 64KB 0x00_1C07_FFFF S/NS
UART0, PL011 0x00_1C09_0000 64KB 0x00_1C09_FFFF S/NS
UART1, PL011 0x00_1C0A_0000 64KB 0x00_1C0A_FFFF S/NS
UART2, PL011 0x00_1C0B_0000 64KB 0x00_1C0B_FFFF S/NS
UART3, PL011 0x00_1C0C_0000 64KB 0x00_1C0C_FFFF S/NS
Watchdog, SP805 0x00_1C0F_0000 64KB 0x00_1C0F_FFFF S/NS
Base Platform Power Controller 0x00_1C10_0000 64KB 0x00_1C10_FFFF S/NS
Dual-Timer 0, SP804 0x00_1C11_0000 64KB 0x00_1C11_FFFF S/NS
Dual-Timer 1, SP804 0x00_1C12_0000 64KB 0x00_1C12_FFFF S/NS
Virtio block device 0x00_1C13_0000 64KB 0x00_1C13_FFFF S/NS
Virtio Plan 9 device 0x00_1C14_0000 64KB 0x00_1C14_FFFF S/NS
Virtio net device 0x00_1C15_0000 64KB 0x00_1C15_FFFF S/NS
Real-time Clock, PL031 0x00_1C17_0000 64KB 0x00_1C17_FFFF S/NS
CF Card, unimplemented 0x00_1C1A_0000 64KB 0x00_1C1A_FFFF S/NS
Color LCD Controller, PL111 0x00_1C1F_0000 64KB 0x00_1C1F_FFFF S/NS
Non-trusted ROM, nontrustedrom 0x00_1F00_0000 4KB 0x00_1F00_0FFF S/NS
CoreSight™ and peripherals 0x00_2000_0000 128MB 0x00_27FF_FFFF S/NS
REFCLK CNTControl, Generic Timer 0x00_2A43_0000 64KB 0x00_2A43_FFFF S
EL2 Generic Watchdog Control 0x00_2A44_0000 64KB 0x00_2A44_FFFF S/NS
EL2 Generic Watchdog Refresh 0x00_2A45_0000 64KB 0x00_2A45_FFFF S/NS
Trusted Watchdog, SP805 0x00_2A49_0000 64KB 0x00_2A49_FFFF S
TrustZone® Address Space Controller, TZC-400 0x00_2A4A_0000 64KB 0x00_2A4A_FFFF S
REFCLK CNTRead, Generic Timer 0x00_2A80_0000 4KB 0x00_2A80_0FFF S/NS
AP_REFCLK CNTCTL, Generic Timer 0x00_2A81_0000 4KB 0x00_2A81_0FFF S/NS
AP_REFCLK CNTBase0, Generic Timer 0x00_2A82_0000 4KB 0x00_2A82_0FFF S
AP_REFCLK CNTBase1, Generic Timer 0x00_2A83_0000 4KB 0x00_2A83_0FFF S/NS
DMC-400 CFG, unimplemented 0x00_2B0A_0000 64KB 0x00_2B0A_FFFF S/NS
SMMUv3 AEMc 0x00_2B40_0000 1MB 0x00_2B4F_FFFF S/NS
GIC Physical CPU interface, GICCd 0x00_2C00_0000 8KB 0x00_2C00_1FFF S/NS
GIC Virtual Interface Control, GICHd 0x00_2C01_0000 4KB 0x00_2C01_0FFF S/NS
GIC Virtual CPU Interface, GICVd 0x00_2C02_F000 8KB 0x00_2C03_0FFF S/NS
CCI-400 0x00_2C09_0000 64KB 0x00_2C09_FFFF S/NS
Non-trusted SRAM 0x00_2E00_0000 64KB 0x00_2E00_FFFF S/NS
GICv3 IRI GICDd 0x00_2F00_0000 64KB 0x00_2F00_FFFF S/NS
GICv3 IRI GITSd 0x00_2F02_0000 128KB 0x00_2F03_FFFF S/NS
GICv3 IRI GICRd 0x00_2F10_0000 1MB 0x00_2F1F_FFFF S/NS
PCIe config regionc 0x00_4000_0000 256MB 0x00_4FFF_FFFF S/NS
PCIe memory region 1c 0x00_5000_0000 256MB 0x00_5FFF_FFFF S/NS
Trusted Random Number Generator 0x00_7FE6_0000 4KB 0x00_7FE6_0FFF S
Trusted Non-volatile counters 0x00_7FE7_0000 4KB 0x00_7FE7_0FFF S
Trusted Root-Key Storage 0x00_7FE8_0000 4KB 0x00_7FE8_0FFF S
DDR3 PHY, unimplemented 0x00_7FEF_0000 64KB 0x00_7FEF_FFFF S/NS
HD LCD Controller, PL370 0x00_7FF6_0000 64KB 0x00_7FF6_FFFF S/NS
DRAM, 0GB-2GB 0x00_8000_0000 2GB 0x00_FFFF_FFFF P
DRAM, 2GB-32GB 0x08_8000_0000 30GB 0x0F_FFFF_FFFF P
PCIe memory region 2c 0x40_0000_0000 256GB 0x7F_FFFF_FFFF S/NS
DRAM, 32GB-512GB 0x88_0000_0000 480GB 0xFF_FFFF_FFFF P

Note:

The BaseR platform copies its memory map from the Base platform, but swaps the upper 2GB of address space with the lower 2GB. Therefore any peripherals in the memory range [0x0-0x7FFFFFFF] in Base are available at the same offset in the memory range [0x80000000-0xFFFFFFFF] in BaseR. Any peripherals in the memory range [0x80000000-0xFFFFFFFF] in Base are available at the same offset in the memory range [0x0-0x7FFFFFFF] in BaseR. The DRAM in the Base platform memory map starts at address 0x80000000, which in BaseR would prevent any code from running from DRAM after reset. The code would be prevented from running because in the Arm®v8‑R architecture the upper 2GB of memory does not have execution permissions by default.

3.4.3 Base - DRAM

The multiple DRAM regions do not alias each other and form a contiguous 512GB area. The total amount of DRAM on the Base Platform system model is configurable. This ability affects where usable DRAM appears.

If the Base Platform system model has bp.dram_size=4, the default, then 2GB of DRAM is accessible at 0x00_8000_0000 to 0x00_FFFF_FFFF, and the remaining 2GB is accessible at 0x08_8000_0000 to 0x08_FFFF_FFFF.

If, instead, the Base Platform system model has bp.dram_size=8, then 2GB of DRAM is accessible at 0x00_8000_0000 to 0x00_FFFF_FFFF and the remaining 6GB is accessible at 0x08_8000_0000 to 0x09_FFFF_FFFF.

The default contents of RAM not otherwise written by the simulation is a repeating sequence of the following 64-bit value: 0xCFDFDFDFDFDFDFCF.

a Non-Secure Access IDentity.
b The device is implemented as RAM and is 8MB in size.
c  Base Platform RevC only
d  You can configure the address of this region using parameters to the model. See the parameters in section GICv3IRI component of Peripheral components in the Fast Models Reference Manual.
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