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This component is an integrated PCIe subsystem which forms part of the Base Platform RevC. It incorporates an SMMUv3, a PCIe, and two PCI devices which wrap a pair of virtio PCI block devices. This model is written in LISA+.
BasePlatformPCIRevC is composed of the following model
The bridge from the Programmer's View bus to the PCI bus.
A wrapper around the underlying virtio block device. There are two block devices in the system, 0 and 1.
The instances of the virtio block device component.
Some interesting options are:
If the following options are set to non-zero values, they print messages about the operation of the bridge. The higher the value, the more verbose the component is:
pci.pvbus2pci.diagnostics=0x0 # (int) default = '0x0': Diagnostics level: [0x0..0x4] pci.pcidevice<N>.diagnostics=0x0 # (int) default = '0x0': Diagnostics level: [0x0..0x4]
Each PCI device uses three BARs; one for config space, one for the MSI-X table structure and one for the MSI-X Pending Bit Array. Each of these can be configured to be 32 bits or 64 bits wide.
The Bus and Device number can be configured for each PCI device. If the device advertises MSI-X, support can be configured.
pci.pcidevice<N>.bus=0x0 # (int ) default = '0x0' : Bus number for this device : [0x0..0xFF] pci.pcidevice<N>.device=0x0 # (int ) default = '0x0' : Device number on this bus : [0x0..0x1F] pci.pcidevice<N>.bar0_64bit=0 # (bool) default = '0' : If BAR 0 is 64 bits wide, if region size is nonzero pci.pcidevice<N>.msix_support=0 # (bool) default = '0' : Enable device support for MSI-X pci.pcidevice<N>.bar2_64bit=0 # (bool) default = '0' : If BAR 2 is 64 bits wide, if region size is nonzero pci.pcidevice<N>.bar4_64bit=0 # (bool) default = '0' : If BAR 4 is 64 bits wide, if region size is nonzero
The following option configures the image file that the virtio block device exposes:
pci.pcivirtioblockdevice<N>.image_path="" # (string) default = '' : image file path
There are two
PVBusLoggers in the
pvbus2pci component. One is in front of the
Configuration space and one is in front of the Device space:
There is one
PVBusLogger in the
component. This reports on DMA accesses by the PCI device:
There is a
PVBusLogger downstream of the SMMU. This
reports on the transactions after they have been transformed by the
For example, you can see all accesses to device space by adding the following options to the command line:
--plugin GenericTrace.so -C TRACE.GenericTrace.trace-sources="FVP_Base_AEMv8A_AEMv8A-PCI.pci.pvbus2pci.devicelogger.*"
Table 3-1 BasePlatformPCIRevC ports
||PVBus||Slave||Input port to service transactions based on the PVBus protocol.|
||PVBus||Master||Output port to send out PVBus transactions that are not handled by this component.|
||Signal||Slave||Input port to handle reset signals. It is used to reset the internal state of this component.|
||Signal||Peer||Port to send out a notification of the occurrence of an event as sg::Signal to a peer.|
||Signal||Master||Array of output ports of type sg::Signal to send out interrupts generated by this component.|
||PVBus||Master||Output port to send out any DMA (of PVBus protocol) accesses originating from this component.|
||ClockSignal||Slave||Input port to connect to a ClockSignal provider.|
Table 3-2 BasePlatformPCIRevC parameters
|Name||Type||Allowed values||Default value||Description|
||The ITS0 Base address.|
When appropriately enabled, assume that MSIs that are generated by the SMMU are presented to the GIC with this DeviceID.