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Home > Programming Reference for VE FVPs > Differences between the VE hardware and the system model > Memory aliasing |
The model implements address-space aliasing of the DRAM. This means that the same physical memory locations are visible at different addresses.
The lower 2GB of the DRAM is accessible at 0x00_80000000
. The full 4GB of DRAM is accessible at 0x08_00000000
and again at 0x80_00000000
. The
aliasing of DRAM then repeats from 0x81_00000000
up to
0xFF_FFFFFFFF
.