5.6.5 Restrictions on the processor models

Some general restrictions apply to the Fixed Virtual Platform implementations of Arm® processors.

  • The simulator does not model cycle timing. In aggregate, all instructions execute in one processor master clock cycle, except for Wait For Interrupt.
  • Write buffers are not modeled on all processors.
  • Most aspects of TLB behavior are implemented in the models. In Armv7 models and later, the TLB memory attribute settings are used when stateful cache is enabled.
  • No device-accurate MicroTLB is implemented.
  • A single memory access port is implemented. The port combines accesses for instruction, data, DMA, and peripherals. Configuration of the peripheral port memory map register is ignored.
  • All memory accesses are atomic and are performed in Programmer’s View (PV) order. Unaligned accesses are always performed as byte transfers.
  • Some instruction sequences are executed atomically so that system time does not advance during their execution. This difference in behavior can affect sequential access of device registers where devices are expecting time to move on between each access.
  • Interrupts are not taken at every instruction boundary.
  • Integration and test registers are not implemented.
  • Not all CP14 debug registers are implemented on all processors.
  • Breakpoint types that the model supports directly are:

    • Single address unconditional instruction breakpoints.
    • Single address unconditional data breakpoints.
    • Unconditional instruction address range breakpoints.
  • Pseudoregisters in the debugger support processor exception breakpoints. Setting an exception register to a nonzero value stops execution on entry to the associated exception vector.
  • Performance counters are not implemented on all models.
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