|Home > Getting Started with Fixed Virtual Platforms > Using the CLCD window|
When a Base or VE FVP starts, the CLCD window opens, representing the contents of the simulated color LCD frame buffer. It automatically resizes to match the horizontal and vertical resolution that is set in the CLCD peripheral registers.
The top section of the CLCD window displays the status information.
Eight white boxes show the state of the User DIP switches.
These represent switch S6 on the VE hardware, USERSW[8:1], which is
mapped to bits [7:0] of the SYS_SW register at address
The switches are in the off position by default. To change its state, click in the area above or below a white box.
Eight white boxes show the state of the VE Boot DIP switches.
These represent switch S8 on the VE hardware, BOOTSEL[8:1], which is
mapped to bits [15:8] of the SYS_SW register at address
The switches are in the off position by default.
Eight colored boxes indicate the state of the VE User LEDs.
These represent the red/yellow/green LEDs on the VE hardware, which are mapped to bits [7:0] of the SYS_LED register at address
Eight white boxes show the state of the daughterboard DIP switches and eight colored boxes show the state of the daughterboard LEDs.
A counter showing the total number of instructions executed.
Because the FVP models provide a Programmer’s View (PV) of the system, the CLCD displays total instructions rather than total processor cycles. Timing might differ substantially from the hardware because:
In general, bus transaction timing is consistent with the hardware, but the timing of operations within the model is not accurate.
A counter showing the total elapsed time, in seconds.
This time is wall clock time, not simulated time.
A feature that disables or enables fast simulation.
Because the system model is highly optimized, your code might run faster than it would on real hardware. This effect might cause timing issues.
Rate Limit is enabled by default. Simulation time is restricted so that it more closely matches real time.
To disable or enable Rate Limit, click the square button. You can configure this option when instantiating the model with the
rate_limit-enable visualization component parameter.
When you click the Total Instr item in the CLCD, the display toggles to show the following:
The number of instructions that execute per second of wall clock time.
You can reset the simulation counters by resetting the model.
The FVP CLCD displays the core run state for each core on each cluster using a colored icon. The icons are to the left of the Total Instr (or Inst/sec) item.
Table 2-1 Core run state icon descriptions
||Run status unknown, that is, simulation has not started.|
||Core running, is not idle, and is executing instructions.|
||External halt signal asserted.|
||Last instruction executed was WFE and standby mode has been entered.|
||Last instruction executed was WFI and standby mode has been entered.|
||External reset signal asserted.|
||Partial core power down.|
||Complete core power down.|
If the CLCD window has focus:
You can hide the host mouse pointer by pressing the left Ctrl+left Alt keys. Press the keys again to redisplay the host mouse pointer. Only the left Ctrl key is operational. The right Ctrl key does not have the same effect.
If you prefer to use a different key, configure it with the
visualization component parameter.