Arm® Cortex®-M55 Processor Technical Reference Manual

Revision r0p1

Table of Contents

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1 Introduction
1.1 Cortex®-M55 processor overview
1.2 Cortex®-M55 features
1.3 Supported standards and specifications
1.4 Design tasks
1.5 Documentation
1.6 Product revisions
2 Technical overview
2.1 Cortex®-M55 processor components
2.1.1 Cortex®-M55 processor core
2.1.2 Extension Processing Unit
2.1.3 Memory components
2.1.4 Interrupt components
2.1.5 Debug and trace components
2.2 Interfaces
2.3 Security
2.4 Reliability
2.5 Power intent
2.6 Cortex®-M55 implementation options
3 Programmers model
3.1 Security states, operation, and execution modes
3.2 Instruction set summary
3.3 Exclusive monitor
3.4 Cortex®-M55 processor core registers summary
3.5 Architectural registers
3.6 Exceptions
3.6.1 Exception handling and prioritization
4 System registers
4.1 System control register summary
4.2 Identification register summary
4.2.1 Media and VFP Feature Register reset values, MVFR0, MVFR1, and MVFR2 reset values
4.3 AFSR, Auxiliary Fault Status Register
4.4 CPUID, CPUID Base Register
4.5 Cache identification register summary
4.5.1 CLIDR, Cache Level ID Register
4.5.2 CSSELR, Cache Size Selection Register
4.5.3 CCSIDR, Cache Size ID Register
4.6 REVIDR, Revision ID Register
4.7 Implementation control register summary
4.8 ACTLR, Auxiliary Control Register
4.9 ICTR, Interrupt Controller Type Register
4.10 IMPLEMENTATION DEFINED registers summary
4.11 Direct cache access registers
4.11.1 DCAICLR and DCADCLR, Direct Cache Access Location Registers
4.11.2 DCAICRR and DCADCRR, Direct Cache Access Read Registers
4.12 Error bank registers
4.12.1 IEBR0 and IEBR1, Instruction Cache Error Bank Register 0-1
4.12.2 DEBR0 and DEBR1, Data Cache Error Bank Register 0-1
4.12.3 TEBR0 and TEBR1, TCM Error Bank Register 0-1
4.13 MSCR, Memory System Control Register
4.14 PAHBCR, P-AHB Control Register
4.15 PFCR, Prefetcher Control Register
4.16 Power mode control registers
4.16.1 CPDLPSTATE, Core Power Domain Low Power State Register
4.16.2 DPDLPSTATE, Debug Power Domain Low Power State Register
4.17 Processor configuration information registers
4.17.1 CFGINFOSEL, Processor configuration information selection register
4.17.2 CFGINFORD, Processor configuration information read data register
4.18 ID_PFR0, Processor Feature Register 0
4.19 ITCMCR and DTCMCR, TCM Control Registers
4.20 TCM security gate registers
4.20.1 ITGU_CTRL and DTGU_CTRL, ITGU and DTGU Control Registers
4.20.2 ITGU_CFG and DTGU_CFG, ITGU and DTGU Configuration Registers
4.20.3 ITGU_LUTn and DTGU_LUTn, ITGU and DTGU Look Up Table Registers
4.21 EWIC interrupt status access registers
4.21.1 EVENTSPR, Event Set Pending Register
4.21.2 EVENTMASKA and EVENTMASKn, n=0-14, Wakeup Event Mask Registers
5 Initialization
5.1 Initialization overview
5.2 Initializing and reprogramming the MPU
5.3 Initializing the EPU
5.4 Programming the SAU
5.5 Initializing the instruction and data cache
5.5.1 Enabling the instruction and data cache
5.5.2 Powering down the caches
5.5.3 Powering up the caches
5.6 Enabling the branch cache
5.7 Enabling and preloading the TCM
5.8 Enabling and locking the TCM security gates
5.9 Enabling the P-AHB interface
6 Power management
6.1 Power domains
6.2 Power states
6.3 Power and operating mode transitions
6.3.1 Operating mode transitions which change PDRAMS power state
6.4 Core P-Channel and power mode selection
6.4.1 P-Channel interface tie-off when P-Channel is not used
6.5 COREPACTIVE and required power mode
6.5.1 COREPACTIVE signal encoding
6.6 PDCORE low-power requirements
6.7 PDEPU low-power requirements
6.8 PDRAMS powerdown requirements
6.9 Warm reset power mode
6.10 Debug Q-Channel and PDDEBUG power domain
6.11 Q-Channel clock control
7 Memory model
7.1 Memory map
7.2 Memory types
7.3 Private Peripheral Bus
7.4 Unaligned accesses
7.5 Access privilege level for Device and Normal memory
7.6 Memory ordering and barriers
7.7 Execute Only Memory
8 Memory Authentication
8.1 MAU features
8.2 Security Attribution Unit
8.2.1 SAU register summary
8.2.2 Security levels
8.3 Memory Protection Unit
8.3.1 Memory Protection Unit register summary
8.4 Implementation Defined Attribution Unit
8.4.1 IDAU interface and backwards compatibility
8.5 Memory regions not controlled by SAU and IDAU
8.6 Security attribution signals
8.7 TCM Gate Units
8.8 TCM and P-AHB security access control
8.8.1 Memory aliasing and IDAU/SAU configuration
8.8.2 Security access gating using the TGU
8.8.3 TGU configuration
8.8.4 Security check and fault response
9 Memory system
9.1 Memory system features
9.2 Memory system faults
9.2.1 Classes of fault
9.3 Memory system behavior
9.3.1 Speculative accesses
9.3.2 Access privilege level for Device and Normal memory
9.4 Master-AXI interface
9.4.1 High performance M-AXI configuration
9.4.2 Area optimized M-AXI configuration
9.4.3 Bridging to AHB
9.4.4 Write response
9.4.5 Memory system implications for AXI accesses
9.4.6 Master-AXI interface transfers
9.5 Peripheral AHB interface
9.5.1 P-AHB interface transfers
9.5.2 P-AHB interface configuration
9.5.3 P-AHB considerations
9.6 S-AHB interface
9.6.1 S-AHB memory map
9.6.2 S-AHB transfers
9.6.3 S-AHB interface arbitration
9.6.4 S-AHB availability and low power states
9.7 EPPB interface
9.8 TCM interfaces
9.8.1 TCM configuration
9.8.2 TCM transactions
9.8.3 Booting from TCM
9.8.4 Integration with flash memory
9.8.5 System access to TCM through the S-AHB DMA interface
9.9 Instruction and data cache
9.9.1 L1 data cache
9.9.2 L1 instruction cache
9.9.3 Cache maintenance operations
9.9.4 Automatic cache invalidation at reset
9.9.5 Cache coherency
9.9.6 Accessing the caches
9.9.7 System cache support
9.9.8 Direct cache access
9.10 Store buffer
9.10.1 Store buffer merging
9.10.2 Store buffer behavior
9.10.3 Store buffer ordering
9.10.4 Store buffer draining
9.11 Internal local exclusive access monitor
9.12 M-AXI and P-AHB interaction with the global exclusive monitor
9.13 MBIST
10 Reliability, Availability, and Serviceability Extension support
10.1 Cortex®-M55 processor implementation of RAS
10.1.1 Cortex®-M55 RAS events
10.2 ECC memory protection behavior
10.2.1 ECC schemes and error type terminology
10.2.2 Enabling ECC
10.2.3 Error detection and processing
10.2.4 Error reporting
10.2.5 Address decoder protection and white noise protection
10.3 Interface protection behavior
10.4 RAS memory barriers
10.5 RAS Extension registers
10.5.1 ERRFR0, RAS Error Record Feature Register
10.5.2 ERRSTATUS0, RAS Error Record Primary Status Register
10.5.3 ERRADDR0 and ERRADDR20, RAS Error Record Address Registers
10.5.4 ERRMISC10, Error Record Miscellaneous Register 10
10.5.5 ERRGSR0, RAS Fault Group Status Register
10.5.6 ERRDEVID, RAS Error Record Device ID Register
10.5.7 RFSR, RAS Fault Status Register
11 Nested Vectored Interrupt Controller
11.1 NVIC features
11.2 Registers associated with interrupt control and behavior
11.3 NVIC register summary
11.4 Software Interrupt Generation register summary
11.5 SysTick Timer register summary
12 External coprocessors
12.1 External coprocessors features
12.2 Operation
12.3 Data transfer rates
12.4 Coprocessor instruction restrictions
12.5 Debug access to coprocessor registers usage constraints
12.6 Exceptions and context switch
12.7 Response to coprocessor errors
12.8 Hazard between load and store instructions followed by coprocessor transactions
13 Floating-point and MVE support
13.1 Floating-point and MVE operation
13.1.1 EPU views of the register bank
13.1.2 Modes of operation
13.1.3 Compliance with the IEEE 754 standard
13.1.4 Exceptions
13.2 Floating-point and MVE register summary
13.3 FPDSCR and FPSCR register reset values
13.4 Powering down the EPU
14 Debug
14.1 Debug functionality
14.1.1 CoreSight™ discovery
14.1.2 Debugger actions for identifying the processor
14.1.3 Processor ROM table identification and entries
14.1.4 Debug identification block register summary
14.1.5 Debug register summary
14.2 D-AHB interface
14.2.1 Debug memory access
14.2.2 Debugger access memory attributes and data cache access
14.2.3 Debug access security and attributes
14.2.4 Debug during reset and before code execution commences
14.2.5 Advanced DSP debug capabilities
15 Performance Monitoring Unit Extension
15.1 PMU features
15.2 PMU events
15.3 PMU register summary
16 Instrumentation Trace Macrocell
16.1 ITM features
16.2 ITM register summary
16.3 ITM_TPR, ITM Trace Privilege Register
16.4 ITM_ITCTRL, ITM Integration Mode Control Register
16.5 ITM_ITWRITE, Integration Write Register
16.6 ITM_ITREAD, Integration Read Register
17 Data Watchpoint and Trace
17.1 DWT features
17.2 DWT debug access control
17.3 DWT comparators
17.4 Cycle counter and profiling counters
17.5 DWT register summary
18 Cross Trigger Interface
18.1 CTI features
18.2 CTI register summary
18.3 CTI_CONTROL, CTI Control Register
18.4 CTI_INACK, CTI Interrupt Acknowledge Register
18.5 CTI_APPSET, CTI Application Channel Set Register
18.6 CTI_APPCLR, CTI Application Channel Clear Register
18.7 CTI_APPPULSE, CTI Application Channel Pulse Register
18.8 CTI_INEN<n>, n=0-5, CTI Trigger <n> to Channel Enable Register
18.9 CTI_OUTEN<n>, n=0-7, CTI Channel <n> to Trigger Enable Register
18.10 CTI_TRIGINSTATUS, CTI Trigger Input Status Register
18.11 CTI_TRIGOUTSTATUS, CTI Trigger Output Status Register
18.12 CTI_CHINSTATUS, CTI Channel Input Status Register
18.13 CTI_CHOUTSTATUS, CTI Channel Output Status Register
18.14 CTI_CHANNELGATE, CTI Channel Gate Register
18.15 CTI_ITCHOUT, Integration Test Channel Output Register
18.16 CTI_ITTRIGOUT, Integration Test Trigger Output Register
18.17 CTI_ITCHIN, Integration Test Channel Input Register
18.18 CTI_ITTRIGIN, Integration Test Trigger Input Register
18.19 CTI_ITCONTROL, Integration Mode Control Register
18.20 CTI_DEVARCH, Device Architecture Register
18.21 CTI_DEVID, Device Configuration Register
18.22 CTI_DEVTYPE, Device Type Identifier Register
18.23 CTI_PIDR4, Peripheral Identification Register 4
18.24 CTI_PIDR5, Peripheral Identification Register 5
18.25 CTI_PIDR6, Peripheral Identification Register 6
18.26 CTI_PIDR7, Peripheral Identification Register 7
18.27 CTI_PIDR0, Peripheral Identification Register 0
18.28 CTI_PIDR1, Peripheral Identification Register 1
18.29 CTI_PIDR2, Peripheral Identification Register 2
18.30 CTI_PIDR3, Peripheral Identification Register 3
18.31 CTI_ CIDR0, Component Identification Register 0
18.32 CTI_ CIDR1, Component Identification Register 1
18.33 CTI_ CIDR2, Component Identification Register 2
18.34 CTI_ CIDR3, Component Identification Register 3
19 Breakpoint Unit
19.1 BPU features
19.2 BPU register summary
A External Wakeup Interrupt Controller
A.1 EWIC features
A.2 EWIC register summary
A.2.1 EWIC_CR, EWIC Control Register
A.2.2 EWIC_ASCR, EWIC Automatic Sequence Control Register
A.2.3 EWIC_CLRMASK, EWIC Clear Mask Register
A.2.4 EWIC_NUMID, EWIC Event Number ID Register
A.2.5 EWIC_MASKA and EWIC_MASKn, EWIC Mask Registers
A.2.6 EWIC_PENDA and EWIC_PENDn, EWIC Pend Event Registers
A.2.7 EWIC_PSR, EWIC Pend Summary Register
A.2.8 EWIC CoreSight™ register summary
A.2.9 EWIC_CLAIMSET, EWIC Claim Tag Set Register
A.2.10 EWIC_CLAIMCLR, EWIC Claim Tag Clear Register
B Trace Port Interface Unit
B.1 TPIU features
B.1.1 TPIU Formatter
B.1.2 Serial Wire Output format
B.2 TPIU register summary
B.2.1 TPIU_SSPSR, Supported Port Size Register
B.2.2 TPIU_CSPSR, Current Port Size Register
B.2.3 TPIU_SPPR, Selected Pin Protocol Register
B.2.4 TPIU_PSCR, Periodic Synchronization Counter Register
B.2.5 TPIU_ACPR, Asynchronous Clock Prescaler Register
B.2.6 TPIU_FFSR, Formatter and Flush Status Register
B.2.7 TPIU_FFCR, Formatter and Flush Control Register
B.2.9 ITFTTD0, Integration Test FIFO Test Data 0 Register
B.2.10 ITATBCTR2, Integration Test ATB Control Register 2
B.2.11 ITFTTD1, Integration Test FIFO Test Data 1 Register
B.2.12 ITATBCTR0, Integration Test ATB Control 0 Register
B.2.13 TPIU_ITCTRL, Integration Mode Control
B.2.14 CLAIMSET, Claim Tag Set Register
B.2.15 CLAIMCLR, Claim Tag Clear Register
B.2.16 TPIU_DEVID, Device Configuration Register
B.2.17 TPIU_DEVTYPE, Device Type Identifier Register
B.2.18 TPIU_PIDR4, Peripheral Identification Register 4
B.2.19 TPIU_PIDR5, Peripheral Identification Register 5
B.2.20 TPIU_PIDR6, Peripheral Identification Register 6
B.2.21 TPIU_PIDR7, Peripheral Identification Register 7
B.2.22 TPIU_PIDR0, Peripheral Identification Register 0
B.2.23 TPIU_PIDR1, Peripheral Identification Register 1
B.2.24 TPIU_PIDR2, Peripheral Identification Register 2
B.2.25 TPIU_PIDR3, Peripheral Identification Register 3
B.2.26 TPIU_ CIDR0, Component Identification Register 0
B.2.27 TPIU_ CIDR1, Component Identification Register 1
B.2.28 TPIU_ CIDR2, Component Identification Register 2
B.2.29 TPIU_ CIDR3, Component Identification Register 3
C Signal descriptions
C.1 Clock and clock enable signals
C.2 Reset signals
C.3 Static configuration signals
C.4 Reset configuration signals
C.5 Instruction execution control signals
C.6 Instruction Tightly Coupled Memory interface signals
C.7 Data Tightly Coupled Memory interface signals
C.8 M-AXI interface signals
C.8.1 M-AXI interface protection signals
C.9 S-AHB interface signals
C.9.1 S-AHB interface protection signals
C.10 P-AHB interface signals
C.10.1 P-AHB interface protection signals
C.11 D-AHB interface signals
C.11.1 D-AHB interface protection signals
C.12 EPPB interface signals
C.12.1 EPPB interface protection signals
C.13 External coprocessor interface signals
C.14 Debug interface signals
C.15 P-Channel and Q-Channel power control signals
C.16 Q-Channel clock control signals
C.17 Power compatibility control signals
C.18 ITM interface signals
C.19 ETM interface signals
C.20 Trace synchronization and trigger signals
C.21 CTI interface signals
C.22 Interrupt signals
C.23 WIC interface signals
C.24 Event signals
C.25 IDAU interface signals
C.26 Miscellaneous signals
C.27 Error interface signals
C.28 Floating-point exception signals
C.29 Test interface signals
C.30 Reserved signals
D.1 Use of instructions defined in architecture variants
D.2 Use of Program Counter - R15 encoding
D.3 Use of Stack Pointer - as a general-purpose register R13
D.4 Register list in load and store multiple instructions
D.5 Exception-continuable instructions
D.6 Stack limit checking
D.7 UNPREDICTABLE instructions within an IT block
D.8 Memory access and address space
D.9 MPU programming
D.10 Miscellaneous UNPREDICTABLE instruction behavior
E Revisions
E.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
0000-02 07 June 2019 Confidential First beta release for r0p0
0000-04 20 December 2019 Confidential First limited access release for r0p0
0001-05 31 March 2020 Non-Confidential First early access release for r0p1

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