3.4.2 IRQ_ENABLE_CLR

Interrupt enable clear register for disabling generation of interrupts for different sources.

The IRQ_ENABLE_CLR register characteristics are:

Usage constraintsThere are no usage constraints.
ConfigurationsThere is only one configuration.
Attributes
Offset0x004
TypeRead-write
Reset0x0
Width32

The following figure shows the bit assignments.

Figure 3-7 IRQ_ENABLE_CLR register bit assignments
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The following list shows the register bit assignments.

[4] READ_OVERFLOW_IRQ_EN_CLR
Disables READ_OVERFLOW_IRQ bit. Write to 1 clears the interrupt enable. Write to 0 has no effect. Reading this bit shows the current status of the enable bit.
[3] CMD_REJECT_IRQ_EN_CLR
Disables CMD_REJECT_IRQ bit. Write to 1 clears the interrupt enable. Write to 0 has no effect. Reading this bit shows the current status of the enable bit.
[2] CMD_FAIL_IRQ_EN_CLR
Disables CMD_FAIL_IRQ bit. Write to 1 clears the interrupt enable. Write to 0 has no effect. Reading this bit shows the current status of the enable bit.
[1] CMD_SUCCESS_IRQ_EN_CLR
Disables CMD_SUCCESS_IRQ bit. Write to 1 clears the interrupt enable. Write to 0 has no effect. Reading this bit shows the current status of the enable bit.
[0] CMD_ACCEPT_IRQ_EN_CLR
Disables CMD_ACCEPT_IRQ bit. Write to 1 clears the interrupt enable. Write to 0 has no effect. Reading this bit shows the current status of the enable bit.
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