A.4 Generic Flash Bus signals

The GFB interface processes several input and output signals.

The following table shows the GFB signals.

Table A-4 Generic Flash Bus signals

Signal name Direction Source or destination Description
faddr[21:0] Output Process‑specific part

Address bus.

Address width is fixed at 22 bits to allow accesses to a 4MB embedded Flash that can be divided into a 2MB main memory and extended memory.

faddr[21] selects between main and extended regions:

0 = Main area.

1 = Extended area.

faddr[3:2] selects the location of the 32‑bit write data within the 128‑bit interface:

0b00 = [31:0].

0b01 = [63:32].

0b10 = [95:64].

0b11 = [127:96].

faddr[1:0] is not used because the minimum data width is 32 bits.

fcmd[2:0] Output Process‑specific part

Command bus:

0b000 = IDLE.

0b001 = READ.

0b010 = WRITE.

0b011 = ROW WRITE.

0b100 = ERASE.

0b101 = Reserved.

0b110 = Reserved.

0b111 = MASS ERASE.

fabort Output Process‑specific part

Abort indication.

When HIGH, the master requests to abort the command that is running.

fwdata[31:0] Output Process‑specific part 32‑bit write data bus.
frdata[127:0] Input Process‑specific part 128‑bit read data bus.
fready Input Process‑specific part

Command ready indication.

Driven LOW if the process‑specific part requires wait states to complete the access.

Driven HIGH when the process‑specific part is ready with the previous access and is able to accept a new command.

fresp Input Process‑specific part

Flash error indication for the previously accepted command.

Driven HIGH for two cycles when an error is indicated for the command that is running.


  • GFB signals that are not shown in the table are not used in GFC-100.
  • The GFC-100 and the GFB slave logic inside the process‑specific part are expected to be in the same power domain. Therefore, the GFB does not require isolation values.
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