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The AHB‑Lite slave interface is a read‑only port through which the system can make read‑only accesses to the embedded Flash. System accesses through the AHB‑Lite slave interface are then transferred over the Generic Flash Bus (GFB).
The data width is fixed at 128 bits. Read accesses that are less than 128 bits are ignored and generate an error response. Write accesses of any size are ignored and generate an error response.
The address of the access does not have to be 128‑bit aligned, because it is forwarded to the GFB directly without any restriction. The Arm® AMBA® Generic Flash Bus Protocol Specification defines that, for wider data widths, the lower address bits are ignored. Therefore, it is implicit that the address is aligned to 128 bits irrespective of what address is sent over the AHB‑Lite slave interface. Although the AHB specification defines that the address must be aligned for all bursts, and single bursts, GFC-100 does not generate an error if an access is not aligned.
The address width is fixed to allow for access to a 4MB memory area. Depending on the attached process‑specific part, the lower 2MB memory region can be a main area, and the upper 2MB region can be an extended area.
The address bus is 22 bits wide. The Most Significant Bit (MSB) can be used to select between the main and extended areas, depending on the attached process‑specific part.
See 3.2.1 AHB-Lite slave interface memory map for a description of the AHB‑Lite slave interface memory map.
Burst transfers are supported to allow large blocks of data to be read from memory. GFC-100 supports all burst types that are specified in the Arm® AMBA® 3 AHB‑Lite Protocol Specification v1.0. Burst transfers ensure that read accesses from the memory have priority above any other commands. Burst transfers are executed at the same speed as commands are executed in the process‑specific part.
The system AHB master can use locked transfers to control the GFC-100 arbitration scheme. Access is granted to the AHB‑Lite slave port only, and all APB accesses are blocked until the entire locked transfer finishes. This ensures that accesses through the AHB‑Lite slave port have deterministic response times.
The response time through the AHB‑Lite slave interface is delayed by asserting the hready signal LOW. The following conditions assert hready:
The following conditions can generate an error response: