A.2 APB slave interface signals

The APB slave interface processes several input and output APB signals.

The following table shows the signals that are used by the APB slave interface.

Table A-2 APB slave interface signals

Signal name Direction Source or destinationa Description
psel_s Input APB bridge

Slave select signal.

Indicates that the current transfer is intended for the Flash controller.

penable_s Input APB bridge

Strobe to time all accesses.

Indicates the start of the second cycle of an APB transfer.

paddr_s[12:0] Input APB bridge

Address bus. paddr_s[12] selects either the internal or an external register bank:

0 = Internal registers.

1 = External registers.

pstrb_s[3:0] Input APB bridge

Write strobe port. Each bit refers to a byte in the pwdata_s signal:

[3] pwdata_s[31:24].

[2] pwdata_s[23:16].

[1] pwdata_s[15:8].

[0] pwdata_s[7:0].

pwrite_s Input APB bridge APB transfer direction. Write only.
pwdata_s[31:0] Input APB bridge 32-bit write data bus.
prdata_s[31:0] Output APB bridge

32-bit read data bus.

Isolation and reset value = 0x00.

pready_s Output APB bridge

Driven LOW when extra wait states are required to complete access to the external registers.

Isolation and reset value = 0b0.

pslverr_s Output APB bridge

Driven HIGH when an error response is received from an access to the external registers.

Isolation and reset value = 0b0.

Note:

APB signals that are not shown in the table are not used in GFC-100.
a The APB bridge is not supplied with GFC-100.
Non-ConfidentialPDF file icon PDF version101059_0000_02_en
Copyright © 2017, 2018 Arm Limited or its affiliates. All rights reserved.