3.4.3 IRQ_STATUS_SET

Interrupt status set register for activating different interrupt sources.

The IRQ_STATUS_SET register characteristics are:

Usage constraintsThere are no usage constraints.
ConfigurationsThere is only one configuration.
Attributes
Offset0x008
TypeRead-write
Reset0x0
Width32

The following figure shows the bit assignments.

Figure 3-8 IRQ_STATUS_SET register bit assignments
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The following list shows the register bit assignments.

[4] READ_OVERFLOW_IRQ_STS_SET
Sets the status of the READ_OVERFLOW_IRQ bit. Write to 1 sets the interrupt. Write to 0 has no effect. Can be used to force the set status of this interrupt bit for debug purposes. Reading this bit shows the current status of the interrupt bit regardless of the interrupt enable setting.
[3] CMD_REJECT_IRQ_STS_SET
Sets the status of the CMD_REJECT_IRQ bit. Write to 1 sets the interrupt. Write to 0 has no effect. Can be used to force the set status of this interrupt bit for debug purposes. Reading this bit shows the current status of the interrupt bit regardless of the interrupt enable setting.
[2] CMD_FAIL_IRQ_STS_SET
Sets the status of the CMD_FAIL_IRQ bit. Write to 1 sets the interrupt. Write to 0 has no effect. Can be used to force the set status of this interrupt bit for debug purposes. Reading this bit shows the current status of the interrupt bit regardless of the interrupt enable setting.

Note:

Write to 1 also sets STATUS.CMD_FAIL.
[1] CMD_SUCCESS_IRQ_STS_SET
Sets the status of the CMD_SUCCESS_IRQ bit. Write to 1 sets the interrupt. Write to 0 has no effect. Can be used to force the set status of this interrupt bit for debug purposes. Reading this bit shows the current status of the interrupt bit regardless of the interrupt enable setting.

Note:

Write to 1 also sets STATUS.CMD_SUCCESS.
[0] CMD_ACCEPT_IRQ_STS_SET
Sets the status of the CMD_ACCEPT_IRQ bit. Write to 1 sets the interrupt. Write to 0 has no effect. Can be used to force the set status of this interrupt bit for debug purposes. Reading this bit shows the current status of the interrupt bit regardless of the interrupt enable setting.
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