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The APB slave interface enables write and erase access to the main and extended areas of embedded Flash. It also acts as a control port for GFC-100 and the Flash macro.
The APB slave interface programs the internal generic APB registers to enable write, erase, and debug read access to the embedded Flash over the GFB interface.
The APB slave interface allows direct access to an external register interface to configure Flash interface access times. The external register interface might be located in the process‑specific part.
The address width is fixed at 13 bits, to allow for 2 × 4KB address spaces. One 4KB region is for internal registers, and the other 4KB region is for registers in the process‑specific part. The MSB, paddr_s selects either internal or external accesses.
See 3.2.2 APB slave interface memory map for a description of the APB slave interface memory map.
The strobe signals are checked for writes to ensure that all bits are set to 1 to indicate 32‑bit word accesses. Otherwise, the write is ignored and has no effect on the registers. The strobe signals are forwarded to the downstream APB master, because the process‑specific part might support byte accesses.
Accesses to the internal register bank are serviced without delay. The design of the process‑specific register bank determines how much delay can be expected for accesses that target its interface.
APB accesses to the internal register bank always give an OKAY response. For reserved addresses, the data that is returned is 0. The response behavior to external register accesses depends on the implementation of the attached process‑specific register bank. Therefore, any errors that are received on the APB master interface are forwarded through the APB slave interface to the access initiator.