3.4.8 ADDR

Address register for the embedded Flash access.

The ADDR register characteristics are:

Usage constraintsThe value that is written to the ADDR field must be either:
  • 32‑bit aligned for write accesses.
  • 128‑bit aligned for read accesses.
ConfigurationsThere is only one configuration.
Attributes
Offset0x01C
TypeRead/write
Reset0x0
Width32

The following figure shows the bit assignments.

Figure 3-13 ADDR register bit assignments
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The following list shows the register bit assignments.

[21:0] ADDR

The 22-bit wide byte address for the current Flash access, allows 2MB address range for the main area and 2MB address range for the extended area.

The ADDR[21] bit selects between memory ranges:

  • 0: Main area.
  • 1: Extended area.

When selecting the extended area for MASS ERASE command, both main and extended areas are cleared. Otherwise, only the main area is cleared. The contents of the extended area remain unchanged after the MASS ERASE finishes.

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