3.3 Register summary

The following table shows the registers in offset order from the base memory address.

Table 3-1 Register summary

Offset

Name

Type

Reset

Width

Description

0x000

IRQ_ENABLE_SET

RW

0x0

32

3.4.1 IRQ_ENABLE_SET

0x004

IRQ_ENABLE_CLR

RW

0x0

32

3.4.2 IRQ_ENABLE_CLR

0x008

IRQ_STATUS_SET

RW

0x0

32

3.4.3 IRQ_STATUS_SET

0x00C

IRQ_STATUS_CLR

RW

0x0

32

3.4.4 IRQ_STATUS_CLR

0x010

IRQ_MASKED_STATUS

RO

0x0

32

3.4.5 IRQ_MASKED_STATUS

0x014

CTRL

RW

0x0

32

3.4.6 CTRL

0x018

STATUS

RO

0x0

32

3.4.7 STATUS

0x01C

ADDR

RW

0x0

32

3.4.8 ADDR

0x020

DATA0

RW

0x0

32

3.4.9 DATA0

0x024

DATA1

RO

0x0

32

3.4.10 DATA1

0x028

DATA2

RO

0x0

32

3.4.11 DATA2

0x02C

DATA3

RO

0x0

32

3.4.12 DATA3

0xFD0

PIDR4

RO

0x4

32

3.4.13 PIDR4

0xFE0

PIDR0

RO

0x32

32

3.4.14 PIDR0

0xFE4

PIDR1

RO

0xB8

32

3.4.15 PIDR1

0xFE8

PIDR2

RO

0xB

32

3.4.16 PIDR2

0xFEC

PIDR3

RO

0x0

32

3.4.17 PIDR3

0xFF0

CIDR0

RO

0xD

32

3.4.18 CIDR0

0xFF4

CIDR1

RO

0xF0

32

3.4.19 CIDR1

0xFF8

CIDR2

RO

0x5

32

3.4.20 CIDR2

0xFFC

CIDR3

RO

0xB1

32

3.4.21 CIDR3

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