A.5 Q-Channel interface for clock signals

The Q‑Channel interface for clock processes all Q‑Channel clock control signals.

The following table shows the signals that are used by the Q‑Channel interface for clock.

Table A-5 Q‑Channel interface for clock signals

Signal name Direction Source or destination Description
qreqn_clk Input Clock controller

Quiescence request. Active‑LOW.

Synchronized with double‑flop synchronizer.

qacceptn_clk Output Clock controller

Accept quiescence request. Active‑LOW.

Isolation and reset value = 0b0.

qdeny_clk Output Clock controller

Deny quiescence request. Active‑HIGH.

Isolation and reset value = 0b0.

qactive_clk Output Clock controller Activity indication. Active‑HIGH.

Driving signals

The system clock controller might be in a different clock or power domain to GFC-100. Therefore, the Q‑Channel interface for clock is considered to be fully asynchronous. This means that a double‑flop synchronizer captures the input signal. Registers drive all output signals.

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