3.4.5 IRQ_MASKED_STATUS

Interrupt status register that shows if each interrupt is pending and is the cause of the interrupt line being asserted.

The IRQ_MASKED_STATUS register characteristics are:

Usage constraintsThere are no usage constraints.
ConfigurationsThere is only one configuration.
Attributes
Offset0x010
TypeRead-only
Reset0x0
Width32

The following figure shows the bit assignments.

Figure 3-10 IRQ_MASKED_STATUS register bit assignments
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The following list shows the register bit assignments.

[4] READ_OVERFLOW_IRQ
When this bit reads 1, it means that READ_OVERFLOW_IRQ is the cause of the interrupt line being asserted.
[3] CMD_REJECT_IRQ
When this bit reads 1, it means that CMD_REJECT_IRQ is the cause of the interrupt line being asserted.
[2] CMD_FAIL_IRQ
When this bit reads 1, it means that CMD_FAIL_IRQ is the cause of the interrupt line being asserted.
[1] CMD_SUCCESS_IRQ
When this bit reads 1, it means that CMD_SUCCESS_IRQ is the cause of the interrupt line being asserted.
[0] CMD_ACCEPT_IRQ
When this bit reads 1, it means that CMD_ACCEPT_IRQ is the cause of the interrupt line being asserted.
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