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The GFC-100 system interface comprises several system I/O ports that are separate from its interfaces.
GFC-100 generates an interrupt request that indicates to the system master that an important event in GFC-100 has occurred. The interrupt is active‑HIGH. It is cleared by accessing registers in GFC-100, and acknowledging the reason for the interrupt, see 3.4.4 IRQ_STATUS_CLR.
When the P‑Channel master sets the embedded Flash power to ON, GFC-100 asserts the flash_pwr_rdy signal. This signal is sent to the process‑specific part GFB slave so that it can initiate any start‑up sequence that requires the embedded Flash to be fully functional.
All the other interfaces operate without any restrictions. The transfers from the AHB‑Lite slave interface are forwarded to the GFB, but transfers are blocked when the command ready indication signal fready is pulled LOW until the initialization finishes.